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| D at a She et , DS8 , Sep te mb er 20 00 ANIC A n a lo g N e t w o r k I n te r fa c e C ir c u it PSB 4450 Version 1.2 PSB 4451 Version 1.2 W ir e d C o m mu n i ca t io n s Never stop thinking. Edition 2000.09.04 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany (c) Infineon Technologies AG 5. 9. 00. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. D at a She et , DS8 , Sep te mb er 20 00 PSB 4450 Version 1.2 PSB 4451 Version 1.2 W ir e d C o m mu n i ca t io n s Never stop thinking. P re li m in ar A n a lo g N e t w o r k I n te r fa c e C ir c u it y ANIC ANIC Preliminary Revision History: Previous Version: Page Page 15 Page 17 Page 22 Page 36 Page 51 Page 92 2000.09.04 Data Sheet DS7 DS8 Subjects (major changes since last revision) Table "Pin Descriptions PSB 4450" on Page 15: "LINE-" connected to pin 1, "LINE+" connected to pin 2 Table "Pin Descriptions PSB 4451" on Page 17: tRESET,min changed from 500 ns to 300 ns, fDATCLK min. changed from 256 kHz to 512 kHz Figure "Voice Path" on Page 22: ANIC-D loop removed Chapter "Data Loops" on Page 36: ANIC-D loop removed, description changes Table "Register Overview" on Page 51: register index 0, offset 10: bit 2 CIF_LOOP renamed to ANIC-A_LOOP Chapter "RESET (Basic Setting Mode)" on Page 92 : tRESET,min changed from 500 ns to 300 ns. Chapter "IDLE Mode" on Page 92: note added Chapter "CONVERSATION Mode" on Page 94: description added Table "Selectable Values for R" on Page 96: values modified Table "Ringer Impedance" on Page 98: values modified Table "DC Characteristics PSB 4450" on Page 102: conditions for supply current changed Table "DC Characteristics PSB 4451" on Page 104: condition on 5 V tolerance added, values and conditions for supply current changed, internal pull-up resistor ranges added (footnote) Test conditions partially modified Chapter "Input/ Output Waveform for AC Tests" on Page 122: figure and description changes Chapter "Reset Timing" on Page 122: figure and description changes Figure "Serial Control Interface Timing" on Page 123: minor changes Table "Serial Control Interface Switching Characteristics" on Page 124: value and description for tD(DOUT_Z) and other parameters changed, parameter DCLK frequency added, note on pull-up resistor added, sentence about DCLK in header added Figure "PCM Interface Timing" on Page 125: minor changes, note added Table "PCM Interface Switching Characteristics" on Page 126: values and description for tSU(DATIN), tHD(DATIN) and tD(DATOUT_Z) changed, note on pull-up resistor added, parameters DATCLK clock frequency and FSC frequency added, tSU(FSC) min. changed to 4*TMCLK Page 94 Page 96 Page 98 Page 102 Page 104 Page 106 Page 122 Page 122 Page 123 Page 124 Page 125 Page 126 For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com PSB 4450 / PSB 4451 ANIC Table of Contents 1 1.1 2 2.1 2.2 3 3.1 4 4.1 4.2 4.2.1 4.3 4.3.1 4.3.2 4.3.3 4.4 4.5 4.6 4.7 4.8 4.9 4.9.1 4.9.2 4.9.2.1 4.9.2.2 4.10 4.11 4.11.1 4.12 5 5.1 5.2 5.2.1 5.3 5.3.1 5.3.1.1 5.3.1.2 5.4 6 Page Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pin Descriptions PSB 4450 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Pin Descriptions PSB 4451 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ANIC Chip Set in the Central Office Terminal (COT) . . . . . . . . . . . . . . . . . 19 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voice Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ring Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Measurement Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tone Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Metering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ring Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt-Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Static Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ANIC Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Support Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sample Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM Interface Timing Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming of ANIC via the Serial Control Interface . . . . . . . . . . . . . Example for Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example for Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Isolation Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 20 21 21 21 23 23 23 23 24 24 25 25 26 26 27 27 33 36 36 36 36 38 38 39 43 45 47 48 49 50 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Data Sheet 5 2000.09.04 PSB 4450 / PSB 4451 ANIC Table of Contents 6.1 6.1.1 6.1.2 7 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.3.1 7.2.4 7.2.5 7.3 7.3.1 7.4 8 8.1 8.2 8.2.1 8.2.2 8.2.3 8.3 8.3.1 8.4 8.4.1 8.4.2 9 9.1 9.2 9.3 9.3.1 9.3.2 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 9.4.7 9.4.8 Data Sheet Page Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Detailed Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Modes of ANIC System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET (Basic Setting Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDLE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RING Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RING - Automatic State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . ON-HOOK CONVERSATION Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . ON-HOOK RECEIVE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Off-hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CONVERSATION Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PULSE COMMAND Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Ranges for DC Termination . . . . . . . . . . . . . . . . . . . . . . Line Current in PULSE COMMAND Mode . . . . . . . . . . . . . . . . . . . . . . AC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ringer Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ring Detect Levels and Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . On-hook and Off-hook Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PSB 4450 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PSB 4451 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Transmission Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Gain Error Off-hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Gain Error On-hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain Tracking Off / On-hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Idle Channel Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Out of Band Idle Channel Noise at TIP/RING . . . . . . . . . . . . . . . . . . . Harmonic Distortion plus Noise Off-hook . . . . . . . . . . . . . . . . . . . . . . . Harmonic Distortion plus Noise On-hook . . . . . . . . . . . . . . . . . . . . . . . Harmonic Distortion Off-hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 91 91 92 92 92 92 92 94 94 94 94 94 95 95 95 95 96 97 98 98 98 98 99 100 100 101 102 102 104 106 106 107 108 108 109 110 110 111 2000.09.04 PSB 4450 / PSB 4451 ANIC Table of Contents Page 111 112 112 113 114 115 115 116 117 117 117 119 120 120 121 122 122 122 123 125 9.4.9 Harmonic Distortion On-hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.10 Total Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.10.1 Total Distortion Measured with Sine Wave . . . . . . . . . . . . . . . . . . . 9.4.10.2 Total Distortion Measured with Noise According to CCITT . . . . . . . 9.4.11 Return Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.12 Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.12.1 Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.12.2 Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.13 Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.13.1 Group Delay Absolute Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.13.2 Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.14 Out-of-Band Signals at TIP-RING Receive . . . . . . . . . . . . . . . . . . . . . 9.4.15 Out-of-Band Signals at TIP-RING Transmit . . . . . . . . . . . . . . . . . . . . . 9.4.16 Trans-Hybrid Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.17 Metering Detection Sensibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5 AC Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.1 Input/ Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.2 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.3 Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.4 PCM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 11 12 13 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Data Sheet 7 2000.09.04 PSB 4450 / PSB 4451 ANIC List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Data Sheet Page Block Diagram of the ANIC Chip Set . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pinning Diagram PSB 4450 (ANIC-A) . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pinning Diagram PSB 4451 (ANIC-D) . . . . . . . . . . . . . . . . . . . . . . . . . 14 ANIC Application in a COT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Functional Block Diagram of the PSB 4450/PSB 4451 Chip Set . . . . . 20 Voice Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC Measurement Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Interrupts on the pins SI0, SI1, RINGIND/SIOD0 and SIOD1 . . . . . . . 28 Ring Interrupt by Detection of a Voltage above a Threshold . . . . . . . . 29 Ring Interrupt by Detection of Valid Ring . . . . . . . . . . . . . . . . . . . . . . . 30 Ring Signal Detection in ANIC-A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Metering Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Tone Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Example for Consecutive Tone Interrupts . . . . . . . . . . . . . . . . . . . . . . 34 Threshold Interrupt: TIP-RING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Example for Consecutive Threshold Interrupts . . . . . . . . . . . . . . . . . . 35 Time Slots for 8 k Sampling Mode and SCI-Clock 2048 kHz. . . . . . . . 41 Time Slots for 16 k Sampling Mode and SCI-Clock 2048 kHz. . . . . . . 41 Time Slots for 16 k Sampling Mode and SCI-Clock 1024 kHz. . . . . . . 42 Time Slots for 16 k Sampling Mode and SCI-Clock 512 kHz. . . . . . . . 42 Example for Single Clock Rate, 512 kb/s. . . . . . . . . . . . . . . . . . . . . . . 43 Mapping of Linear and Companded Data into PCM Slots for 8 kHz . . 43 Mapping of Linear Data into PCM Slots for 16 kHz . . . . . . . . . . . . . . . 44 PCM Interface Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Example for a Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Example for a Read Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Isolation by Capacitive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Isolation by Inductive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Ring Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 DC Termination Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 DC Characteristics for France . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Gain Tracking Off / On-hook (Receive or Transmit). . . . . . . . . . . . . . 108 Out of Band Idle Channel Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Total Distortion Receive or Transmit . . . . . . . . . . . . . . . . . . . . . . . . . 112 Total Distortion Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Total Distortion Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Return Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Frequency Response Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Frequency Response Transmit (HPX is off) . . . . . . . . . . . . . . . . . . . 116 Group Delay Distortion Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Group Delay Distortion Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 8 2000.09.04 PSB 4450 / PSB 4451 ANIC List of Figures Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Page 119 120 121 121 122 122 123 125 Out of Band Receive Discrimination . . . . . . . . . . . . . . . . . . . . . . . . . Out of Band Transmit Discrimination . . . . . . . . . . . . . . . . . . . . . . . . . Metering Detection Sensibility 16 kHz (Typical). . . . . . . . . . . . . . . . . Metering Detection Sensibility 12 kHz (Typical). . . . . . . . . . . . . . . . . Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet 9 2000.09.04 PSB 4450 / PSB 4451 ANIC List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Page Pin Descriptions PSB 4450 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Pin Descriptions PSB 4451 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PCM Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 kHz Sampling Rate (8 k sampling mode, fFSC = 8 kHz) . . . . . . . . . 40 16 kHz Sampling Rate (16 k sampling mode, fFSC = 8 kHz) . . . . . . . 40 SCI-Clock, FSC, Sampling Mode and Time Slot Interdependency . . . 40 Serial Control Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 CRAM Definitions for Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 CRAM Definitions for Coefficients (see Table 9) . . . . . . . . . . . . . . . . . 55 RAM Definitions for Coefficients (see Table 12) . . . . . . . . . . . . . . . . . 55 RAM Definitions for Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Measurement Result Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Selectable Values for ILIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Selectable Values for U0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Selectable Values for R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 DC Characteristics PSB 4450 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 DC Characteristics PSB 4451 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Serial Control Interface Switching Characteristics . . . . . . . . . . . . . . 124 PCM Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 126 Data Sheet 10 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Overview 1 Overview ANIC is a chip set to interface analog voice signals to digital terminals such as DSL transceivers. Its technology and design make it especially suitable for the use throughout the world for applications such as * DAML (Digital Added Main Line) interface between a central office and digital line transceivers, * PBX trunks, * Universal DLC (Digital Loop Carrier) systems. RESET MCLK VDD GND VDDA GNDA PCM Interface Serial = Control Interface (SCI) GPIO PSB 4451 (ANIC-D) Digital Isolation Interface TIP-RING PSB 4450 (ANIC-A) GPIO Figure 1 Block Diagram of the ANIC Chip Set Note: The block diagram is described in more detail in the section "Functional Description" on Page 20. The ANIC chip set is an ideal analog front end to convert digital information into analog signals and vice versa for communication via telephone lines. Reliability in digital processing is much better than in analog communications. The new design of the ANIC chip set has transferred processing that was previously done on the analog side to the digital part. Digital filters ensure great precision and virtually no fluctuation. The use of digital filter processing in combination with software algorithms ensures excellent transmission performance and adaptability. The ANIC chip set is programmable to adapt to different countries' requirements. Coefficient sets can be downloaded to the ANIC chip set to comply with specifications throughout the world. Data Sheet 11 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Overview The ANIC chip set replaces the traditional Data Access Arrangement (DAA) with voice band transformer and discrete components. The use of digital signal processing and filtering approaches provides the user not only more features and programmability, but also better system performance. As a result of the Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) technology used, the linearity of the ANIC chip set is limited only by second-order parasitic effects. The main functional blocks of the ANIC are: * * * * Data Access Arrangement (DAA) Selectable A-law, -law, and 16-bit linear coder/decoder (codec) TIP-RING-GROUND voltage measurements to identify, e.g., polarity reversal Time slot assignment for PCM-highway interface The technology used for the two chips is: * PSB 4450 (analog) low-power 0.8 m BiCMOS * PSB 4451 (digital) 0.35 m CMOS Infineon Technologies offers a range of reference and evaluation tools for the ANIC chip set. For appropriate tools, please contact your nearest Infineon Technologies representative. Data Sheet 12 2000.09.04 Preliminary Analog Network Interface Circuit ANIC PSB 4450 PSB 4451 Version 1.2 1.1 Features * The ANIC chip set replaces the traditional Data Access Arrangement (DAA), codec and hybrid components. * On-hook transmission. * DC measurements of TIP-RING, RING-GROUND and TIP-GROUND voltage. * General purpose I/O pins. * Works with a large range of clock frequencies from 16.384 MHz to 33 MHz. * Supports sample rates from 6 kHz up to 24 kHz * 3 V technology for the PSB 4451. - Output pins are TTL and CMOS compatible. - Input pins are 5 V tolerant. * On chip VDD control for the PSB 4450. International features: P-TSSOP-38-1 P-TSSOP-28-1 * Programmable ring detection: country-specific frequencies and levels. Coefficients for frequencies and levels are downloadable. * Programmable country-specific DC characteristics. * Detection of metering signals. * PCM encoded digital voice transmission (A-Law or -Law) according G.711. Type PSB 4450 PSB 4451 Data Sheet Package P-TSSOP38 P-TSSOP28 13 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Pin Descriptions 2 Pin Descriptions LINE LINE + VREF TIP_AC RING_AC CAP1 CAP2 GNDA TIP_RG RING_RG RG_AC TEST SO3Q SO2 SO1Q SO0 B22 B21 A22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 S2 S3 T1G T2G T3G T4G SOH T5G VDDA SENS M1 M2 M3 SI0 SI1 NC C21 C22 A21 ezm24003.wmf Figure 2 Pinning Diagram PSB 4450 (ANIC-A) A12 B11 B12 NC NC NC RINGIND / SIOD0 SIOD1 DCDCCLK CS DCLK DOUT DIN INT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A11 C12 C11 VDD GND RESET METIND / SOD0 NC MCLK1 NC DATCLK DATIN DATOUT FSC ezm24004.wmf Figure 3 Pinning Diagram PSB 4451 (ANIC-D) Data Sheet 14 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Pin Descriptions 2.1 Table 1 Pin No. 30 3 8 1 2 9 10 4 5 11 38 37 16 15 14 13 12 25 24 36 35 34 33 31 11 29 32 Pin Descriptions PSB 4450 Pin Descriptions PSB 4450 Symbol VDDA VREF GNDA LINELINE+ TIP_RG RING_RG TIP_AC RING_AC RG_AC S2 S3 SO0 SO1Q SO2 SO3Q TEST SI0 SI1 T1G T2G T3G T4G T5G NC SENS SOH Power I I I I I I I I I O O O O I I I O O O O O I I Function Description Power + 5 V supply for analog circuitry Filtering reference voltage Ground analog. All signals are referenced to this pin. Voltage sense input from TIP Voltage sense input from RING Voltage sense input for ringing Voltage sense input for ringing Voltage sense input for AC signals Voltage sense input for AC signals Voltage sense input for AC signals in ON-HOOK CONVERSATION mode Sense inputs for ringer impedance loop Sense inputs for ringer impedance loop General purpose output General purpose output General purpose output General purpose output Must be connected to GND General purpose input General purpose input Control pin for transistor T1 Control pin for transistor T2 Control pin for transistor T3 Control pin for transistor T4 Control pin for transistor T5 unused Voltage sense for VDD control Current sensing for on-hook transmission Data Sheet 15 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Table 1 Pin No. 28 27 26 6 7 20 Pin Descriptions PSB 4450 (Continued) Symbol M1 M2 M3 CAP1 CAP2 A21 Function Description I I I O O I Measurement input GROUND Measurement input TIP Measurement input RING External low pass filter External low pass filter Digital isolation interface to PSB 4451: Must be connected to pin A11 of PSB 4451 (see Page 50) Digital isolation interface to PSB 4451: Must be connected to pin A12 of PSB 4451 (see Page 50) Digital isolation interface to PSB 4451: Must be connected to pin B11 of PSB 4451 (see Page 50) Digital isolation interface to PSB 4451: Must be connected to pin B12 of PSB 4451 (see Page 50) Digital isolation interface to PSB 4451: Must be connected to pin C11 of PSB 4451 (see Page 50) Digital isolation interface to PSB 4451: Must be connected to pin C12 of PSB 4451 (see Page 50) unused Pin Descriptions 19 A22 I 18 B21 O 17 B22 O 22 C21 I 21 C22 I 23 NC - Note: For further details see Application Note "Understanding the External Components of the ANIC Chip Set". Data Sheet 16 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Pin Descriptions 2.2 Table 2 Pin No. 25 24 20 23 Pin Descriptions PSB 4451 Pin Descriptions PSB 4451 Symbol VDD GND MCLK1 RESET Function Description Power Power I I + 3.3 Volt supply for the digital & analog circuitry. Ground digital. All signals are referenced to this pin. Master Clock1: this pin must be driven by an external clock of e.g. 16.384 MHz Reset input: resets the device (low active) Reset is considered valid if asserted active longer than tRESET,min = 300 ns . Frame Synchronization Clock PCM Interface: receive data 8-bit timeslots. PCM Interface: transmit data, tristate if not active Data clock 512 to 2048 kHz: determines the rate at which data is transferred to and from the PCM Interface. Interrupt output pin (open drain, low active, internal pull up with 32 kOhm). Serial Control Interface: clock for control data. Serial Control Interface: chip select Serial Control Interface: receive control data from the C / DSP Serial Control Interface: transmit control data to the C / DSP Output for DCDC switching clock Digital isolation interface to PSB 4450: Must be connected to pin A21 of PSB 4450 (see Page 50) Digital isolation interface to PSB 4450: Must be connected to pin A22 of PSB 4450 (see Page 50) 15 17 16 18 FSC DATIN DATOUT DATCLK I I O I 14 11 10 13 12 9 28 INT DCLK CS DIN DOUT DCDCCLK A11 O I I I O O O 1 A12 O Data Sheet 17 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Table 2 Pin No. 2 Pin Descriptions PSB 4451 (Continued) Symbol B11 Function Description I Digital isolation interface to PSB 4450: Must be connected to pin B21 of PSB 4450 (see Page 50) Digital isolation interface to PSB 4450: Must be connected to pin B22 of PSB 4450 (see Page 50) Digital isolation interface to PSB 4450: Must be connected to pin C21 of PSB 4450 (see Page 50) Digital isolation interface to PSB 4450: Must be connected to pin C22 of PSB 4450 (see Page 50) Metering indication or general purpose output pin (active high). General purpose I/O pin. Ring indication or general purpose I/O pin (active high). Unused Unused Unused Unused Unused Pin Descriptions 3 B12 I 26 C11 O 27 C12 O 22 8 7 6 21 19 4 5 METIND / SOD0 SIOD1 RINGIND / SIOD0 NC NC NC NC NC O IO IO - - - - - Data Sheet 18 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Typical Applications 3 Typical Applications As mentioned in the overview, one of the ANIC applications is in central office terminals (COT) serving as interface between voice signals of the CO's analog line card and the digital line transceivers connected to the network. In typical implementations, the innovative digital isolation interface renders a transformer redundant, reducing weight and space requirements. 3.1 ANIC Chip Set in the Central Office Terminal (COT) The ANIC chip set forms the front end between a MDSL chip set and the TIP-RING line. PCM-2 TIP-RING MDSL-D PEB22521 PSB 4451 PSB 4450 TIP-RING Digital Isolation Interface PSB 4451 PSB 4450 TIP-RING SCI (CI) C ===========C = Microcontroller SCI (CI) = Serial Control Interface Figure 4 ANIC Application in a COT The MDSL chip set is both source and destination of digital signals which are transferred to and from the digital chip PSB 4451 via the PCM Interface. The Serial Control Interface (SCI) enables external control of the ANIC chip set. The SCI gives transparent access to ANIC commands and signalling pins so that precalculated coefficient sets can be downloaded from the system to the on-chip coefficient RAM (CRAM) to program the filters. Data Sheet 19 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Functional Description 4 Functional Description The functional description consists of a block diagram with explanation of the building blocks followed by a description of the chip set's basic principles of operation. 4.1 Functional Block Diagram The chip set consists of two chips, PSB 4450 and PSB 4451. Figure 5 shows the main building blocks: Control Data Digital Isolation Interface Control GPIO CI GPIO Control VDD Control DSP HWFilter A/D Hybrid and Filters D/A PCM PSB 4451 PSB 4450 VDD TIP/RING Transmit/Receive Data ezm24000.wmf Figure 5 PSB 4450: Functional Block Diagram of the PSB 4450/PSB 4451 Chip Set VDD Control: regulates the supply voltage for the PSB 4450 and can be connected to an isolated 5 V or by the use of an external transistor to an unregulated DC voltage (VDD). Hybrid and Filters: the hybrid provides two-wire to four-wire conversion, and the analog anti-aliasing pre-filters and smoothing post-filters provide signal conditioning. The voice data path is routed from the filters to the digital isolation interface through the Analog-to-Digital (A/D) or the Digital-to-Analog (D/A) converters: These are oversampling converters based on a - modulation approach. The oversampling technique provides signals with low signal-to-noise ratio and high conversion resolution. Digital Isolation Interface: Used for isolation of PSB 4451 from PSB 4450. General Purpose I/Os (GPIOs): PSB 4450 has 2 inputs (SI0, SI1) and 2 outputs (SO2, SO3Q). The inputs can be used as interrupt sources. The outputs can be used to control external switches for the connection of terminal impedance. Data Sheet 20 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary PSB 4451: Hardware filters: The HW filters are interpolating transmit and decimating receive digital filters. See also Figure 6 for details. Digital Signal Processing Unit (DSP): The DSP does equalization, gain adjustment, impedance matching, and other DAA functions, in accordance with the downloaded coefficient set. PCM Interface: Via the PCM Interface transmit and receive data are transferred between the PSB 4451 and the digital transceiver (e.g. MDSL chip set). Serial Control Interface (SCI): The Serial Control Interface allows external control of the ANIC features and provides transparent access to ANIC commands and signalling pins, so that pre-calculated coefficient sets can be downloaded from the system to the on-chip Coefficient RAM (CRAM) to program the filters. General Purpose I/Os (GPIOs): PSB 4451 has two input/output pins (SIOD1, RINGIND/ SIOD0) and one output pin (METIND/SOD0) to control external components. Functional Description 4.2 4.2.1 General Description Impedance ANIC requires an external transistor T1 to control the DC and AC loop current. T1 must be able to handle 100 mA of continous current. On the TIP/RING side, ANIC applies voltage sensing and current feeding. There is a feedback loop between the receive and the transmit path to synthesize input impedance. This means the voltage is multiplied by a transfer function and fed back as a current to the line. This transfer function synthesizes the ANIC input impedance for AC, DC and RING. Within that functionallity, the ANIC acts as the required passive network. 4.3 Voice Path These filters are programmable according to the selected specification by downloading the appropriate sets of coefficients. The converted signal is available at the PCM output every 125 s. Decoding can be either selected according G.711 (A- / -law) or 16-bit linear 2s complement. Similarly, digital data in the transmit direction are shifted in and processed by programmable filters for the selected specification. The results are sent to the interpolating transmit filter and are converted to an analog signal by the oversampling D/A converter. Figure 6 shows the voice path through the digital filter structure. Some filters are fixed while others are user programmable. Data Sheet 21 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Functional Description Digital out HPR AR1 FRR RFIX1 AR2 RFIX2 ADC LM METD ANIC-A Loop THFIX PCM Loop TH IMFIX HY TIP RING IM Digital in HPX AX1 FRX XFIX1 AX2 XFIX2 DAC Digital Isolation Interface ANIC-D ANIC-A Legend: HY AR1 FRR RFIX1 AR2 RFIX2 ADC THFIX TH user-programmable block fixed filter block fixed functional block IMFIX IM AX1 Hybrid Amplification Receive Filter 1 Equalization Receive Receive Filter Fixed Part 1 Amplification Receive Filter 2 Receive Filter Fixed Part 2 Analog-to-Digital Converter Transhybrid Filter Fixed Part Transhybrid Filter Impedance Filter Fixed Part Impedance Filter Amplification Transmit Filter 1 Equalization Transmit Transmit Filter Fixed Part 1 Amplification Transmit Filter 2 Transmit Filter Fixed Part 2 Digital-to-Analog Converter Level Metering Metering Detection High Pass Transmit High Pass Receive Definition: Transmit: Digital-to-Analog Receive: Analog-to-Digital FRX XFIX1 AX2 XFIX2 DAC LM METD HPX HPR Figure 6 Voice Path Data Sheet 22 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Functional Description 4.3.1 Receive Path The analog signal proceeds from TIP/RING to PSB 4450 with an anti-aliasing pre-filter. The Analog-to-Digital Converter (ADC) is a sigma-delta converter, which converts the signal to a 1-bit digital data stream. The signal is then passed to the PSB 4451 where the first stage of down-sampling is performed in hardware, for better performance, in the digital filter RFIX2. Subsequent stages of processing are done by microcode in the digital filter structure, to allow adaptability. Gain adjustment is provided in the two stages AR1 and AR2. The switchable high pass HPR is used to suppress low frequent noise. A decimation stage is located inbetween to reduce the sampling rate to the 8/16 kHz PCM rate, and a low-pass filter to band-limit the signal in accordance with ITU-T G.714 and Q.552 recommendations; and an equalization stage (in FRR). Finally, the signal will be A-law or -law coded and transferred out to the PCM Interface. The ANIC meets or exceeds all ITU and ETSI recommendations on attenuation, distortion and group delay. A metering function is included on the receive path. 4.3.2 Transmit Path The digital input signal is received from the PCM Interface and decoded from A-law or -law. Most processing steps are done in microcode in the digital filter structure, which is programmable and therefore flexible. There are two gain adjustment stages, in AX1 and AX2. The switchable high pass HPX is used to suppress low frequent noise. Located inbetween, there is an equalization stage (in FRX), a high-pass filter and a lowpass filter to band-limit the signal (in XFIX1); and a first stage of interpolation. Further up-sampling is done by hardware (in XFIX2), and the 1-bit data stream is converted to analog in the DAC and smoothed by a post-filter, followed by an analog gain stage before the signal is converted to a two-wire signal. 4.3.3 Loops ANIC implementation includes two loops. One is used to generate the AC-termination impedance (IM, IMFIX), the ring impedance and the AC impedance for on-hook transmission and the other is used to perform accurate hybrid balancing (TH, THFIX). 4.4 Ring Path The ringer impedance is synthesized in the same way as the AC impedance using a feedback loop. Data Sheet 23 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Functional Description 4.5 DC Measurement Path To measure the DC voltage between TIP-RING, TIP-GROUND and RING-GROUND, a filter structure similar to that of the voice receive path is used. Each voltage is measured for an interval of 375 s (3 times 1/8000 Hz) and stored in the corresponding register ( 2s complements, see register 7 to register 9). These registers are updated every 1.125 milliseconds. The voltage is measured in four selectable ranges with 8 bit resolution (see register 25) Each measurement provides individual programmable thresholds (registers 19 & 20 for RING-GROUND, registers 21 & 22 for TIP-GROUND and registers 15 to 18 for TIPRING). Any voltage exceeding these thresholds will trigger a maskable interrupt. The measured value can be used to detect line reversal and disconnection of the line. TIP-RING TIP-GROUND RING-GROUND Measurement Registers DCFIX ADC Hybrid TIP-RING TIP-GROUND RING-GROUND Legend: ADC DCFIX Fixed filter block Fixed functional block Analog-to-Digital Converter Decimation Filter for DC Figure 7 DC Measurement Path 4.6 Tone Detection1) ANIC is equipped with two programmable tone detectors to detect modem and CALLER ID alert tones. Both of them can generate an interrupt. 1) Coefficients will be computed by the ANICOS Software. By downloading these coefficients to the ANIC using the ANICON software, the desired functionality will be provided. Data Sheet 24 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Functional Description 4.7 Metering1) Metering frequencies of 12 and 16 kHz are filtered out by the PSB 4451. Signals with level less than 2.5 Vrms can be applied directly to ANIC. However, an external notch filter is necessary to attenuate metering signals that exceed 2.5 Vrms. ANIC is capable of signalling metering information via interrupt. Longitudinal 50 Hz metering can be realized usings ANICs measurement cabability. 4.8 Ring Detect2) ANIC can be programmed to detect ring signals and will indicate them with an interrupt. The ring threshold as well as the ring frequency can be programmed. 1) Coefficients will be computed by the ANICOS Software. By downloading these coefficients to the ANIC using the ANICON software, the desired functionality will be provided. 2) Coefficients will be computed by the ANICOS Software. By downloading these coefficients to the ANIC using the ANICON software, the desired functionality will be provided. Data Sheet 25 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Functional Description 4.9 4.9.1 Interrupt Structure Interrupt-Handling All interrupt sources are polled at a time intervall of at least tFSC = 125 s for FSC = 8 kHz (depending on the load of the controller). That means that an interrupt source must be stable for a minimum of this period to be detected. FSC Int-Source 1 Int-Source 2 Scanning of Interrupt Sources (Exact Moment Depends on Chip-Status) ezm33001.wmf Figure 8 Interrupt Structure In the above example the change of the Int-Source 1 is detected. Int-Source 2 is not detected by the Interrupt-controller and therefore will be ignored. The host can enable the INT output by setting register 2. Following power-up, register 2 is cleared, i.e., all interrupt sources are disabled and INT is in high impedance state. INT, when asserted low, indicates an interrupt. The host reads the register 1 to determine the source of the interrupt. Reading the interrupt status register 1 clears the register content. All interrupt sources have equal priority. Data Sheet 26 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Functional Description 4.9.2 TYPE Static Static Static Static Dynamic Dynamic Interrupt Sources NAME SI0, SI1 RINGIND/ SIOD0, SIOD1 RING MET TONE THRESHOLD MEANING Detection of changes on this GPIs of ANIC-A via the digital isolation interface Detection of changes on this GPIOs of ANIC-D, when they are configured as inputs Detection of ring signal Detection of metering signals by ANIC DSP software Detection of programmed tone Detection if actual programmed threshold value on TIPRING, RING-GROUND or TIP-GROUND has been exceeded. Polling: If all interrupts are disabled in register 2 there is still a possibility to poll the events that otherwise would have caused an indication at the INT pin. The occurence of an interrupt can always be detected by reading the register 1. There are two types of interrupts: 4.9.2.1 Static Interrupts Static interrupts take place on signal changes of the following signals: * Static interrupt sources on pins SI0, SI1, RINGIND / SIOD0 and SIOD1 * Detection of ring signals * Detection of metering signals Every detected signal change is reflected by an logic 1 in the corresponding bit in the register 1. Unlike dynamic interrupts there is also an interrupt produced at the end of the event or signal. Data Sheet 27 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Functional Description Interrupts on the pins SI0, SI1, RINGIND/SIOD0 and SIOD1: Interrupts on the GPI pins SI0 and SI1 use the following bits: * Bits SIA0 and SIA1 in register 5 indicate the value of the pins SI0 and SI1. * Bits SIA0 and SIA1 in register 1 show that a signal on the pins SI0 and SI1 was the cause for an interrupt indication on the INT pin. Reading register 1 sets the INT pin back to inactive (high). For detecting interrupts on the GPIO pins RINGIND/SIOD0 and SIOD1 it is necessary to configure them as inputs in register 10. The following bits are used: * Bits SIOD0_I and SIOD1_I in register 5 indicate the value of the pins RINGIND/SIOD0 and SIOD1. * Bits SIOD0 and SIOD1 in register 1 show that a signal on the pins RINGIND/SIOD0 and SIOD1 was the cause for an interrupt indication on the INT pin. Reading register 1 sets the INT pin back to inactive (high). Figure 9 shows the status of the INT output in relation to the static interrupt sources SIX input pins. SIX pin INT pin Read operation register 1 Read operation register 1 anic_0004_programmableIO.emf Figure 9 Interrupts on the pins SI0, SI1, RINGIND/SIOD0 and SIOD1 Data Sheet 28 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Ring Interrupt: There are two possibilities for ring detection on TIP/RING: 1. Ring interrupt by detection of a voltage above the ring threshold Since only a voltage detection takes place, the validation according to amplitude and frequency of the ring signal has still to be done by the host. The ring interrupt indication on the RINGIND/SIOD0 pin derives from internal signals which allow checking for spike rejection (ring deglitch time, see register 27), suppression of short rings (ring persistance time, see register 26) and ring interruptions (ring timeout, see register 103) as shown in Figure 10. UTIP-RING Functional Description Threshold t Analog ring Internal signals Ring deglitch time Deglitched ring Ring persistance time Switch to RING RINGIND/SIOD0 pin Read operation register 1 Read operation register 1 Ring timeout INT pin anic_0003_ringvaI0.emf Figure 10 Ring Interrupt by Detection of a Voltage above a Threshold Data Sheet 29 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 2. Ring interrupt by detection of valid ring Figure 11 shows a ring interrupt with internal validation in the ANIC according to amplitude and frequency defined by programmed CRAM coefficients. UTIP-RING Functional Description Threshold t Analog ring Ring timeout Internal signals Ring deglitch time Deglitched ring Valid ring Ring persistance time Read operation register 1 RINGIND/SIOD0 pin Read operation register 1 INT pin anic_0002_ringvaI1.emf Figure 11 Ring Interrupt by Detection of Valid Ring According to Figure 12, ring signal detection in ANIC-A causes an automatic transition from the ON-HOOK CONVERSATION or ON-HOOK RECEIVE to the RING state (see register 5). R IN G sig na l de te ction in A N IC -A O N -H O O K C O N V E R S A T IO N O N -H O O K R E C E IV E R IN G anic_0012_ring.emf Figure 12 Data Sheet Ring Signal Detection in ANIC-A 30 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Both possiblities for ring detection use the following bits: * Bit SHOW_RING in register 24 enables the indication of the ring status on pin RINGIND/SIOD0, if this pin is configured as output (register 10). * Bit RING in register 5 indicates if either a voltage above a ring threshold or a valid ring was detected or finished (depending of bit RING_VAL in register 10). * Bit RING in register 1 shows that a ring detection was the cause for an interrupt indication on the INT pin. Reading register 1 sets the INT pin back to inactive (high). Functional Description Data Sheet 31 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Metering Interrupt: Metering interrupts use the following bits: * Bit SHOW_MET in register 24 enables indication of metering signals on pin METIND/ SOD0. * Bit MET in register 1 shows that a metering detection was the cause for an interrupt indication on the INT pin. Reading register 1 sets the INT pin back to inactive (high). The metering interrupt indication on the METIND/SOD0 pin derives from internal signals which allow checking for suppression of short metering signals (metering persistance time, see register 28) and metering signal interruptions (metering timeout, see register 104) as shown in Figure 13. The filter transient ON and OFF times are defined by CRAM settings. Functional Description UTIP-RING Detection of new metering signal possible t Filter transient ON Internal signals Filter transient OFF Metering signal Interrupt source INT pin Metering persistance time Metering timeout Read operation register 1 METIND/SOD0 pin Read operation register 1 anic_0006_met12.emf Figure 13 Metering Interrupt Data Sheet 32 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Functional Description 4.9.2.2 Dynamic Interrupts Dynamic interrupts are caused by the following events: * Detection of tone signals * Passing of programmed threshold voltages at TIP-RING, RING-GROUND and TIP-GROUND. Unlike static interrupts there is no interrupt produced at the end of the event. Every detected event is reflected by a logic 1 in the corresponding bit of register 1 (details in register 2 and register 5). Tone Interrupt: Tone interrupts can be used for fax or modem alert tone detection. The following bits are used: * Bits E_TONE(0) and E_TONE(1) in register 24 enable the detection of the tone sources tone 0 or tone 1. * Bits TONE(0) and TONE(1) in register 5 indicate the detection of the tone sources tone 0 or tone 1. Reading register 5 clears the bits TONE(0) and TONE(1). * Bit TONE in register 1 shows that a tone detection was the cause for an interrupt indication on the INT pin. Reading register 1 sets the INT pin back to inactive (high). The tone interrupt indication on the INT pin derives from internal signals which allow checking for suppression of short metering signals (tone persistance time, see register 28) and tone signal interruptions (tone timeout, see register 104) as shown in Figure 14. The filter transient ON and OFF times are defined by CRAM settings. UTIP-RING Detection of new tone signal possible t Filter transient ON Internal signals Filter transient OFF Tone signal Interrupt source INT pin Tone persistance time Metering timeout Read operation register 1 anic_0005_tone12.emf Figure 14 Data Sheet Tone Interrupt 33 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Functional Description When there are two consecutive tone interrupts (e.g. "INT-A" followed by "INT-B", see Figure 15) and INT-B happens before the interrupt service routine of INT-A could read register 5, the source of INT-B will be read together with the source of INT-A in register 5 (Bits TONE(0) = TONE(1) = 1). As reading register 5 clears the bits TONE(0) and TONE(1), the later starting interrupt service routine of INT-B cant find a source for this interrupt in register 5 (Bits TONE(0) = TONE(1) = 0). Therefore, the host must ignore the interrupt service routine of INT-B and use the values of the former routine. IN T -A INT pin IN T -B IN T -A ro utine : IN T -B ro utine : R e ad o p era tion R e ad o p era tion re gister 1 re gister 1 IN T -A rou tin e: IN T -B ro u tine : R ea d op e ra tio n R e ad op era tion reg iste r 5 , reg iste r 5 , T o ne (0) = T on e(1 ) = 1 T o ne (0) = T o ne (1) = 0 anic_0009_consec_int.emf Figure 15 Example for Consecutive Tone Interrupts Threshold Interrupt: Threshold interrupts can be used to detect line reversal, disconnect or 50 Hz metering signals on TIP-RING, RING-GROUND or TIP-GROUND line voltages. An interrupt is detected, when the line voltage passes a programmable threshold voltage (see registers 15 to 22). TIP-RING, RING-GROUND and TIP-GROUND threshold interrupts use the following bits: * Bits E_TR(x), E_RG(x) and E_TG(x) in register 23 enable the detection of TIP-RING, RING-GROUND or TIP-GROUND line voltage threshold indications. * Bits TR(x), RG(x) and TG(x) in register 4 indicate the TIP-RING, RING-GROUND and TIP-GROUND voltages passing a programmed threshold value. Reading register 4 clears the bits TR(x), RG(x) and TG(x). * Bit THR in register 1 shows that passing a voltage threshold was the cause for an interrupt indication on the INT pin. Reading register 1 sets the INT pin back to inactive (high). Figure 16 shows an example for a TIP-RING threshold interrupt with the threshold voltages TR0 to TR3 (registers 15 to 18). A programmable measurement persistance time (see register 29) helps to avoid threshold indications caused by spikes. UM2-M3 is the voltage between the pins M2 and M3 which derives from TIP and RING. Data Sheet 34 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary UM2-M3 Functional Description TR1 (reg. 16) TR0 (reg. 15) t TR2 (reg. 17) TR3 (reg. 18) INT pin Read operation registers 1 and 4 anic_0001_threshold.emf Figure 16 Threshold Interrupt: TIP-RING When there are two consecutive threshold interrupts (e.g. "INT-A" followed by "INT-B", see Figure 17) and INT-B happens before the interrupt service routine of INT-A could read register 4, the source of INT-B will be read together with the source of INT-A in register 4 (Bits TR(x), RG(x) and TG(x)). As reading register 4 clears the bits TONE(0) and TONE(1), the later starting interrupt service routine of INT-B cant find a source for this interrupt in register 4 (Bits TR(x) = RG(x) = TG(x) = 0). Therefore, the host must ignore the interrupt service routine of INT-B and use the values of the former routine. IN T -A INT pin IN T -B IN T -A ro utine : R e ad o p era tion re gister 1 IN T -B ro utine : R e ad o p era tion re gister 1 IN T -B ro utine : IN T -A rou tin e: R e ad op era tion R ea d op e ra tio n re g ister 4 , reg iste r 4 T R (X ) = R G (x) = T G (x)= 0 anic_0010_consec_int_thres.emf Figure 17 Data Sheet Example for Consecutive Threshold Interrupts 35 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Functional Description 4.10 ANIC Clocking Any master clock frequency between 16.384 MHz and 33 MHz can be used as the ANIC synchronizes to the incoming frame sync (FSC). The DCDCCLK or a synchronous clock should be used to clock a DCDC converter to supply the ANIC-A. This will prevent intermodulation in between the VDDA and the A/D or D/A converters of the ANIC-A. 4.11 4.11.1 Test Modes Data Loops To test the chip datapath the following digital loops are available (see Figure 6): * PCM loop to test the correct connection to the PCM Interface (see bit PCM_LOOP in register 10). The PCM input data will be send back exactly in the next PCM frame. * ANIC-A loop to test the ANIC-A and ANIC-D (see bit ANIC-A_LOOP in register 10). Functional test loop. The functionallity of the ANIC-D and the digital isolation interface of the ANIC-A can be checked. 4.12 Support Package The ANIC can be programmed to pass individual country specific requirements. This can be done by downloading different coefficients into the CRAM using the ANICON control software. For the calculation of these coefficients a coefficent computing program called ANICOS will be provided. The ANICOS software is a project-oriented Windows-based program. On-line help is available and the validity of user inputs checked automatically, enabling users to obtain optimized sets of coefficients to program the ANIC quickly and easily. ANICOS calculates coefficients for the following filters. AC Filters: * Impedance matching to adapt the system to the required line impedance of the local loop (return loss calculation), * Frequency response correction for both receive and transmit paths, * Level adjustment for both receive and transmit paths, * Transhybrid balancing DC Filters: * DC characteristic Data Sheet 36 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Ringing: * Ringer impedance * Ring detect (level and frequency) Miscellaneous: * Ringing signal * Level Metering * Metering signals detection (level and frequency) After defining the required inputs for ANICOS, the user can start calculating the filter coefficients. All calculation results are stored in the result file which can be displayed in the ANICOS program. Some of the calculations are also displayed graphically to enable the product designer to verify the required behaviour quickly, and make any additional optimization manually. The following calculations are displayed graphically: * * * * Return loss, Input impedance, Frequency response in receive and transmit path (locus diagram), Transhybrid loss. Functional Description ANICOS produces both a result file and a byte file. The byte file contains the programming bytes, including the filter coefficients. An important feature of the ANICOS software is the automatic verification of the calculated coefficients against criteria necessary to maintain overall system stability. Data Sheet 37 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Digital Interfaces 5 Digital Interfaces The digital interfaces consist of a Serial Control Interface (SCI) and a PCM Interface. Both interfaces operate up to 2048 kHz. As described in Chapter 4.10, ANIC uses master clock frequencies from 16.384 up to 33 MHz. In this document, functionality is described for fMCLK = 24.576 MHz. 5.1 Sample Rates The internal datapath clock is synchronized to the frame synchronization (FSC) signal. For PCM frame based systems this clock is 8 kHz. In this document, functionalitiy is described using this 8 kHz FSC. However, the ANIC can be synchronized to all frame synchronization (FSC) signals between 6 and 12 kHz, although the used FSC frequencies are in a range between 8 and 12 kHz as shown in Table 6. The FSC limits can be computed: Example: fMCLK = 24.576 MHz, no predivider is used fFSC = fFRAC / 2048 with fFRAC,min = fMCLK / [1+32767/32768] > fMCLK / 2 fFRAC,max = fMCLK / [1+1/65536)] < fMCLK Therefore: Frame sync lower limit: fFSC,min > fMCLK / 4096 = 6 kHz Frame sync upper limit: fFSC,max < fMCLK / 2048 = 12 kHz Within one frame the ANIC can be programmed to provide one (8 k sampling mode) ore two (16 k sampling mode) samples (see register 14, bit 16k). Following power-up ANIC is programmed to the 16-bit linear mode and 8 k sampling mode. If the companding mode is switched on (register 14, bit COMP = 1), ANIC sends and receives the 8 bit A-law companded data on one PCM slot. Using the 16 kHz mode, the PCM decimation filter from 16 to 8 kHz is switched off and four consecutive time slots are used to provide these two samples. Within that mode, only the 16 bit linear data transmission is possible. Data Sheet 38 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Digital Interfaces 5.2 Table 3 DATCLK FSC DATIN DATOUT PCM Interface PCM Interface Pins PCM-Clock, 512 kHz to 2048 kHz Frame Synchronization Clock Receive Voice input for PCM Highway Transmit Voice output for PCM Highway A serial PCM Interface is used for voice transfer. The PCM Interface consists of 4 pins: The data rate of the interface can vary from 512 kb/s to 2048 kb/s. A frame may consist of up to 32 time slots of 8 bits each. Receive and transmit time slots can be programmed individually in normal mode (PCM) and in linear mode. An extra delay of up to 7 clocks, valid for all channels, as well as the sampling slope1) may be programmed. In order to provide high bandwith for modem and fax application also a sample rate of 16 kHz can be programmed. In this mode the ANIC will use four consecutive timeslots for the two 16 kHz linear coded samples within one frame. The frame sync (FSC) input determines the beginning of the receive and transmit time slots. The FSC must have a minimum duration of one DATCLK cycle (see Chapter 9.5.4). The DATCLK clock is the signal to synchronize the voice transfer on both lines DATOUT and DATIN. Bytes in all channels are serialized to 8 bit width (normal mode) or 16 bit width (linear mode) and MSB first. For configuration of the PCM Interface see register 14. Note: In order to avoid bus contention, bit 0 (LSB) at DATOUT is only asserted during the positive half-cycle of DATCLK, and is high-impedance during the negative half-cycle of DATCLK. At power up, the PCM interface is inactive (tri-state condition) until the relevant registers are programmed. Table 4 and Table 5 list the possible clock rates for the PCM Interface at fFSC = 8 kHz. Clock rates such as 768 kHz and 1536 kHz are also supported. Table 6 shows the FSC frequency and number of time slots per PCM frame for a given SCI-clock fDCLK and the 8 k or 16 k sampling mode. Figure 18 to Figure 21 are graphical illustrations of the values in Table 6. Figure 22, Table 4 and Table 5 illustrate the PCM Interface timing and time slots mapping, respectively. Figure 25 shows examples of time slot offset referenced to FSC. The recieve and transmit time slots are offset by the same amount of DATCLK periods. 1) Data can be sampled at the rising or falling edge of the clock. Data Sheet 39 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Table 4 Digital Interfaces 8 kHz Sampling Rate (8 k sampling mode, fFSC = 8 kHz) PCM-Clock Frequency (kHz) 512 1024 2048 Formula f Time Slots (per highway) 8 16 32 f/64 Datarate (kbits/s per highway) 512 1024 2048 f Table 5 16 kHz Sampling Rate (16 k sampling mode, fFSC = 8 kHz) PCM-Clock Frequency (kHz) 512 1024 2048 Time Slots (per highway) 4 8 16 f/128 Datarate (kbits/s per highway) 512 1024 2048 f Formula f Table 6 SCI-Clock, FSC, Sampling Mode and Time Slot Interdependency1) Time Slots per Frame 32 16 8 8 16 8 16 8 see Figure 19 see Figure 20 see Figure 21 see Figure 18 Figure SCI-Clock2) fDCLK (kHz) / maximum Sampling Mode FSC Frequency fFSC (kHz) 8 2048 / 8 k 2048 / 16 k 1024 / 16 k 512 / 16 k 1) 2) 10 12 10 8 11 10 11 for fMCLK = 24.576 MHz Serial Control Interface SCI-Clock on pin DCLK (fDCLK) Data Sheet 40 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Digital Interfaces T im e S lo ts S C I-C lo ck f D C L K = 2 0 4 8 kH z A re a o f p o ssib le T im e S lo ts 32 24 16 8 F S C F re qu e n cy [kH z] 7 8 9 10 11 12 13 anic_0013_8-2048.emf Figure 18 Time Slots for 8 k Sampling Mode and SCI-Clock 2048 kHz T im e S lo ts S C I-C lo ck f D C L K = 2 0 4 8 kH z A re a of p o ssib le T im e S lo ts 32 24 16 8 F S C F re qu e n cy [kH z] 7 8 9 10 11 12 13 anic_0014_16-2048.emf Figure 19 Time Slots for 16 k Sampling Mode and SCI-Clock 2048 kHz Data Sheet 41 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Digital Interfaces T im e S lo ts S C I-C lo ck f D C L K = 1 0 2 4 kH z A re a of p o ssib le T im e S lo ts 32 24 16 8 F S C F re qu e n cy [kH z] 7 8 9 10 11 12 13 anic_0015_16-1024.emf Figure 20 Time Slots for 16 k Sampling Mode and SCI-Clock 1024 kHz T im e S lo ts S C I-C lo ck f D C L K = 5 1 2 kH z A re a of p o ssib le T im e S lo ts 32 24 16 8 F S C F re qu e n cy [kH z] 7 8 9 10 11 12 13 anic_0016_16-512.emf Figure 21 Time Slots for 16 k Sampling Mode and SCI-Clock 512 kHz Data Sheet 42 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Digital Interfaces 5.2.1 PCM Interface Timing Examples 125 s FSC DATCLK DATIN 076 54 32107654321076 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 10 7 6 DATOUT 0 7 6 5 4 32 1 0 7 6 5 4 3 2 10 7 6 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 10 7 6 Voice 0 Voice 1 Voice 6 Voice 7 FSC duration: min. 1 DATCLK clock cycle max. 0.5 FSC clock cycles Figure 22 Example for Single Clock Rate, 512 kb/s For special purposes the DATIN and DATOUT pins may be strapped together, and form a bi-directional datapin. frame n-1 1 (MSB) 2 (LSB) 1 2 3 3 frame n 4 4 5 5 6 6 7 7 8 8 1 1 frame n+1 2 2 Mapping 16bit, Timeslot 1, offset 0 selected Mapping 8bit A or Law, Timeslot 1, offset 0 selected anic_0007_pcm_map8.emf Figure 23 Mapping of Linear and Companded Data into PCM Slots for 8 kHz Data Sheet 43 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary frame n-1 1 (MSB) 2 (LSB) Digital Interfaces frame n 3(MSB) 4(LSB) 5 6 7 8 1 frame n+1 2 Mapping 16bit, Timeslot 1, offset 0 selected 1. Sample 2.Sample anic_0008_pcm_map16.emf Figure 24 Mapping of Linear Data into PCM Slots for 16 kHz Note: Using the 16 kHz sampling mode only the linear mode is availble. e.g. Number of TS is 4, offset is 7 765432107654321076543210765432107654321076543210 RS: XS: 3 3 4 4 1 1 2 2 3 3 4 4 e.g. Number of TS is 4, offset is 0 765432107654321076543210765432107654321076543210 RS: XS: 4 4 1 1 2 2 3 3 4 4 1 1 e.g. Number of TS is 4, offset is 3 765432107654321076543210765432107654321076543210 RS: XS: 4 4 1 1 2 2 3 3 4 4 1 1 Note: the value 00h as RS or XS value disables the PCM interface ! ezm33011.emf Figure 25 Data Sheet PCM Interface Frames 44 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Digital Interfaces 5.3 Serial Control Interface The Serial Control Interface is used to communicate with an external host, e.g., a microcontroller. The internal configuration registers, the auxiliary ports, and the Coefficient RAM (CRAM) of the ANIC are programmable via the Serial Control Interface. This Interface consists of 4 pins: Table 7 CS DCLK DIN DOUT Serial Control Interface Pins Chip select input, for enabling interface (active low) SCI-Clock input, fDCLK = 1 kHz to 2048 kHz Data input Data output The host asserts CS low to initialize a communication with ANIC. Following a falling edge of CS the first 8 bits received at DIN determine the command type. The CLK clocks can be continously running or gated. However, there must be 16 low CLK pulses within the CS low interval to complete a READ or WRITE transaction. CS DCLK DIN 76543210 76543210 Control Data Byte High 'Z' DOUT Figure 26 Example for a Write Access Data Sheet 45 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Digital Interfaces If the first eight bits received via DIN specify a read-command, the ANIC will start to response via DOUT with its specific register byte . CS DCLK DIN 7654321 0 Control High 'Z' DOUT 7 6 5 4 3 2 10 Data Byte Figure 27 Example for a Read Access Note: In order to avoid bus contention, bit 0 (LSB) at DOUT is only asserted during the positive half-cycle of DCLK, and is high-impedance during the negative half-cycle of DCLK. The data transfer is synchronized by DCLK. DIN is latched at the falling edge of DCLK, while DOUT changes with the rising edge of DCLK. During execution of a command which is followed by output data (read command), the device will not accept any new command via DIN. The data transfer sequence can be interrupted by setting CS to high. To reduce the number of connections to the Controller DIN and DOUT may be strapped together to a bidirectional datapin. Data Sheet 46 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Digital Interfaces 5.3.1 Programming of ANIC via the Serial Control Interface CMD command word Bit 1) 7 R/nW 1) 6 I 5 A3 4 A2 3 A1 2 A0 1 1 0 x R/nW is the MSB and will be transferred first. x A[3:0] A[3:0] = 0000 .... A[3:0] = 1111 I I=0 I=1 R/nW R/nW = 0 R/nW = 1 Dont care Offset address for basic and indexed addressing mode. Offset 0 Offset 15 Use of index register Use offset address A[3:0] (Basic addressing mode) Use Index register + offset address A[3:0] (Indexed addressing mode) Read or write data Write Data to ANIC Read data from ANIC * RAM address of Indexregister: 0 256 Byte RAM: 128 Byte CRAM: I = INT (Adr / 16) * 8 O = Adr - 2 * I 0h to FFh 100h to 17Fh (I must be a multiple of 8) (O must be between 0 and 15) * Calculating the Index (I) and Offset (O) out of the C/RAM-address (Adr): Data Sheet 47 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Digital Interfaces 5.3.1.1 Example for Write Operation Write data value FBh to RAM-address AFh = 10101111 First Step: Write Indexregister. * Write Command on DIN: Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 1 0 X * Index on DIN: I = INT (Adr / 16) * 8 = INT (AFh / 16) * 8 = 01010000 = 50h. Bit 7 0 6 1 5 0 4 1 3 0 2 0 1 0 0 0 Second Step: Write data value FBh = 11111011 in indexed addressing mode. * Write Command on DIN: Offset A[3:0] = Adr - 2*I = AFh - 2 * 50h = 1111 Bit 7 0 * Data on DIN: Bit 7 1 6 1 5 1 4 1 3 1 2 0 1 1 0 1 6 1 5 1 4 1 3 1 2 1 1 1 0 X Data Sheet 48 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Digital Interfaces 5.3.1.2 Example for Read Operation Read data from CRAM-address 17Dh = 101111101 First Step: Write Indexregister: * Write Command on DIN: Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 1 0 X * Index on DIN: I = INT (Adr / 16) * 8 = INT (17Dh / 16) * 8 = 10111000 = B8h. Bit 7 1 6 0 5 1 4 1 3 1 2 0 1 0 0 0 Second Step: Read data in indexed addressing mode. * Read Command on DIN: Offset A[3:0] = Adr - 2*I = 17Dh - 2 * B8h = 1101 Bit 7 1 6 1 5 1 4 1 3 0 2 1 1 1 0 X * Data following Read Command on DOUT: Bit 7 d7 6 d6 5 d5 4 d4 3 d3 2 d2 1 d1 0 d0 Data Sheet 49 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Digital Interfaces 5.4 Digital Isolation Interface The isolation between ANIC-A and ANIC-D and therefore from the TIP/RING side to the host/datapump side can be realized in two ways: Capacitive Interface Isolation is realized by six capacitances. The two "A", "B" and "C" capacitors must match to within 5 % of the selected value between 5 to 30 pF. CAP_A1 A11 A12 CAP_A2 CAP_B1 A21 A22 B21 B22 CAP_B2 CAP_C1 B11 B12 C11 C12 CAP_C2 C21 C22 ANIC-D ANIC-A ezm37014.emf Figure 28 Isolation by Capacitive Interface Inductive Interface Isolation is realized by extra small transformers provided by third party. A11 A12 B11 B12 C11 C12 A21 A22 B21 B22 C21 C22 ANIC-D ANIC-A ezm37013.emf Figure 29 Isolation by Inductive Interface Data Sheet 50 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Programming 6 Programming ANIC uses a simple type of 8 bit command structure. To access the configuration registers or configuration RAM index addressing (paging) is used. The index register is located in the 0 page. This page can be programmed directly by setting the bit INDEX to '0'. Register located in other pages can be addressed using the index register and setting the bit INDEX to '1'. 6.1 6.1.1 Register Map Overview All dark grey area is reserved for internal use and must not be addressed by commands. The contents of the light grey area is supplied by Infineon Technologies as coefficients for country specific adaptations. I: Index, O: Offset, T: Type, D: Default Table 8 I 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 8 8 8 O 0 1 2 3 4 5 6 7 8 9 T RW R RW RW R R RW R R R D 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Register Overview MSB Bit7 Index(7) MET E_MET 0 RG(1) MET SOA3 MTR7 MRG7 MTG7 PULSE 0 0 0 16K TR0(7) TR1(7) TR2(7) TR3(7) TG0(7) Bit6 Index(6) RING E_RING 0 RG(0) RING SOA2 MTR6 MRG6 MTG6 CMD_ MODE 0 0 0 OS2 TR0(6) TR1(6) TR2(6) TR3(6) TG0(6) Bit5 Index(5) THR E_THR 0 TG(1) Bit4 Index(4) TONE Bit3 Index(3) SIA1 Bit2 Index(2) SIA0 E_SIA0 State(2) TR(2) SIA0 SOD0 MTR2 MRG2 MTG2 ANIC-A_ LOOP TS2 RS2 XS2 A/MU TR0(2) TR1(2) TR2(2) TR3(2) TG0(2) Bit1 Index(1) SIOD1 E_SIOD1 LSB Bit0 Index(0) SIOD0 E_SIOD0 E_TONE E_SIA1 0 TG(0) State(3) TR(3) State(1) TR(1) SIOD1_I SIOD1_O State(0) TR(0) SIOD0_I SIOD0_O TONE(1) TONE(0) SIA1 SOA1 MTR5 MRG5 MTG5 PCM_ LOOP TS5 RS5 XS5 OS1 TR0(5) TR1(5) TR2(5) TR3(5) TG0(5) SOA0 MTR4 MRG4 MTG4 RING_ VAL TS4 RS4 XS4 OS0 TR0(4) TR1(4) TR2(4) TR3(4) TG0(4) x MTR3 MRG3 MTG3 DCDC TS3 RS3 XS3 COMP TR0(3) TR1(3) TR2(3) TR3(3) TG0(3) MTR1 MRG1 MTG1 SIOD1_ C TS1 RS1 XS1 0 TR0(1) TR1(1) TR2(1) TR3(1) TG0(1) MTR0 MRG0 MTG0 SIOD0_ C TS0 RS0 XS0 EDGE TR0(0) TR1(0) TR2(0) TR3(0) TG0(0) 10 RW 11 RW 12 RW 13 RW 14 RW 15 RW 0 1 2 3 RW RW RW RW Data Sheet 51 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Table 8 I 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 48 48 96 96 O 4 5 6 7 8 9 T RW RW RW RW RW RW D 00h 00h 00h 00h 00h 00h 01h 01h 01h 01h 12h 00h RW RW RW RW RW RW RW RW RW RW 00h 00h Programming Register Overview (Continued) MSB Bit7 TG1(7) RG0(7) RG1(7) E_RG(1) SHOW_ RING 0 RG_ PER(7) RG_ DEG(7) MET_ PER(7) MMPER (7) HW_ VER(3) x x x Bit6 TG1(6) RG0(6) RG1(6) E_RG(0) SHOW_ MET 0 RG_ PER(6) RG_ DEG(6) MET_ PER(6) MMPER (6) HW_ VER(2) x 0 0 Bit5 TG1(5) RG0(5) RG1(5) E_TG(1) Bit4 TG1(4) RG0(4) RG1(4) E_TG(0) Bit3 TG1(3) RG0(3) RG1(3) E_TR(3) Bit2 TG1(2) RG0(2) RG1(2) E_TR(2) x TG0 RG_ PER(2) RG_ DEG(2) MET_ PER(2) MMPER (2) SW_ VER(2) RING_ EXT DC_K0 XAGX_ K0 Bit1 TG1(1) RG0(1) RG1(1) E_TR(1) x TR1 RG_ PER(1) RG_ DEG(1) MET_ PER(1) MMPER (1) SW_ VER(1) HOOK_ CMD DC_U1 RAGR_ K1 LSB Bit0 TG1(0) RG0(0) RG1(0) E_TR(0) TEST_ TONE TR0 RG_ PER(0) RG_ DEG(0) MET_ PER(0) MMPER (0) SW_ VER(0) PCM_ MM DC_U0 RAGR_ K0 E_TONE E_TONE x (1) (0) RG1 RG_ PER(5) RG_ DEG(5) MET_ PER(5) MMPER (5) HW_ VER(1) x DC_K3 0 RG0 RG_ PER(4) RG_ DEG(4) MET_ PER(4) MMPER (4) HW_ VER(0) x DC_K2 0 TG1 RG_ PER(3) RG_ DEG(3) MET_ PER(3) MMPER (3) SW_ VER(3) x DC_K1 XAGX_ K1 10 RW 11 RW 12 RW 13 RW 14 R 15 0 1 2 3 4 5 6 7 8 9 10 RW 11 RW 7 8 RW RW 0Ah 03h 50h 3Ch RING_ TO(7) TONE_ TO(7) 0 ALF RING_ TO(6) TONE_ TO(6) COT2 IM RING_ TO(5 TONE_ TO(5 DHPR2 FRR RING_ TO(4) TONE_ TO(4) MM FRX RING_ TO(3) TONE_ TO(3) FSC16 AR RING_ TO(2 TONE_ TO(2 COT1 AX RING_ TO(1) TONE_ TO(1) COR2 RIP RING_ TO(0) TONE_ TO(0) COR1 0 12 RW 13 RW Data Sheet 52 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Table 8 I 96 96 O T D D8h 10h 00h 00h 00h 00h 00h 00h Programming Register Overview (Continued) MSB Bit7 LPX EN_TB CRAM CRAM CRAM CRAM CRAM CRAM Bit6 LPR 0 CRAM CRAM CRAM CRAM CRAM CRAM Bit5 TG RGS CRAM CRAM CRAM CRAM CRAM CRAM Bit4 LM2 MET_ MMG Bit3 LM1 DHPTH CRAM CRAM CRAM CRAM CRAM CRAM Bit2 LB64 0 CRAM CRAM CRAM CRAM CRAM CRAM Bit1 LBZ DHPR1 CRAM CRAM CRAM CRAM CRAM CRAM LSB Bit0 TH DHPX CRAM CRAM CRAM CRAM CRAM CRAM 14 RW 15 RW RW 128 0 CRAM CRAM CRAM CRAM CRAM CRAM .... RW .... RW 184 0 RW .... RW .... RW Note: Registers 16/2 to 16/11 are for internal use only. Registers 128/0 to 184/15 represent the coefficient RAM address area. CRAM and on-hook CRAM coefficients are shown in Table 9 and Table 12. Coefficients of the same colour can be modified independendly of other coefficients. Data Sheet 53 2000.09.04 Data Sheet 54 2000.09.04 Preliminary Table 9 CRAM Definitions for Coefficients Byte 7/15 Byte 6/14 BA23 B22 B72 R42 Z52 ZH3 RH1 FR42 X42 AR20 BA22 B21 B71 R41 Z51 ZH4 Byte 5/13 BA21 B13 B63 R33 Z43 Z63 BA20 B12 B62 R32 Z42 Z62 Byte 4/12 BA19 B11 B61 R31 Z41 Z61 BA18 FB4 B53 R23 Z33 ZB9 RB9 FR23 X23 AR10 AX22 LT4 LT3 LT2 LT1 QT TN3 TN2 TN1 LA4 T18 T17 T16 T15 T14 T13 T12 T11 X63 G4 MM2 LR53 LX53 G3 MM1 LR52 LX52 G2 MM0 LR51 LX51 G1 K LR43 LX43 MET D4 Z83 LR42 LX42 MET D3 Z82 LR41 LX41 MET D2 Z81 LR33 LX33 MET D1 Z73 LR32 LX32 Q Z72 LR31 LX31 X62 SF Z71 LR23 LX23 X61 BT4 FR53 LR22 LX22 CM5 BT3 FR52 LR21 LX21 CM4 BT2 FR51 LR13 LX13 CM3 BT1 X53 LR12 LX12 CM2 MU2 X52 LR11 LX11 CM1 MU1 X51 176 B0h LA3 LA2 LA1 QA AC3 AC2 AC1 AX21 AX20 AX14 AX13 AX12 AX11 AX10 168 A8h Byte 3/11 BA17 FB3 B52 R22 Z32 ZB8 RB8 FR22 X22 BA16 FB2 B51 R21 Z31 ZB7 RB7 FR21 X21 Byte 2/10 BA15 FB1 B43 R13 Z23 ZB6 RB6 FR13 X13 BA14 FB0 B42 R12 Z22 ZB5 RB5 FR12 X12 Byte 1/9 BA13 BA29 B41 R11 Z21 ZB4 RB4 FR11 X11 BA12 BA28 B33 RM3 Z13 ZB3 RC3 FR03 X03 Byte 0/81) BA11 1) Index Index hex. 128 80h TH1 TH2 TH3 RIP1 IM1 IM2 RIP2 FRR FRX AR AX LM1 LM2 TG RGS METD MMG LPR LPX 1) BA25 HT HP2 --ZH1 RH3 --AR22 BA24 B23 HP1 R43 Z53 ZH2 RH2 FR43 X43 AR21 BA10 1) BA27 1) BA26 1) B32 RM2 Z12 ZB2 RC2 FR02 X02 B31 RM1 Z11 ZB1 RC1 FR01 X01 136 88h 144 90h C_TR C_TR C_TR -3 2 1 FR41 X41 AR14 FR33 X33 AR13 FR32 X32 AR12 FR31 X31 AR11 152 98h 160 A0h PSB 4450 / PSB 4451 ANIC Programming --- 184 B8h For example "Byte 0/8" means: 0 = Offset for byte BA10/BA11 , 8 = Offset for byte BA26/BA27 PSB 4450 / PSB 4451 ANIC Preliminary Table 10 Flagname TH RIP IM FRR FRX AR AX LM TG RGS MET_MMG LPR LPX CRAM Definitions for Coefficients (see Table 9) Coefficient Group Definition TH1, TH2, TH3 RIP1, RIP2 IM1, IM2 FRR FRX AR AX LM1, LM2 TG RGS METD MMG LPR LPX Transhybrid optimization Ring impedance, level metering Line impedance matching Frequency response receive Frequency response transmit Gain in receive direction Gain in transmit direction Level metering Tone generator Level metering frequency response transmit Metering signal detection Multi purpose measurement gain Low pass filter receive Low pass filter transmit Programming The coefficients for transhybrid optimization TH1, TH2 and TH3 (see Table 10) are different in ON-HOOK CONVERSATION and CONVERSATION state. When switching to these states, the host must also download the corresponding coefficients TH1, TH2 and TH3 to the ANIC-D. This has to be done as there is no automatic swapping implemented for this coefficients in the ANIC-D firmware. Table 11 FRR AR RAM Definitions for Coefficients (see Table 12) Usage of Coefficients Frequency response in ON-HOOK RECEIVE state. Gain in ON-HOOK RECEIVE state Coefficients Group Data Sheet 55 2000.09.04 Data Sheet 56 2000.09.04 Preliminary Table 12 RAM Definitions for Coefficients Byte 6 / 14 Byte 5 / 13 Byte 4 / 12 Byte 3 / 11 Byte 2 / 10 Byte 1 / 9 Byte 0 / 81) Index/Offset dec. hex. 50/C 50/E 58/6 Byte 7 / 15 FRR FRR AR 1) FR53 -FR43 FR42 FR41 FR33 FR32 FR31 FR23 FR22 AR22 FR21 AR21 FR13 AR20 FR12 AR14 FR11 AR13 FR52 FR03 AR12 FR51 FR02 AR11 X53 FR01 AR10 80/12 80/14 88/06 For example "Byte 0 / 8" means: 0 = Offset for byte BA10 / BA11 , 8 = Offset for byte BA26 / BA27 PSB 4450 / PSB 4451 ANIC Programming PSB 4450 / PSB 4451 ANIC Preliminary Programming 6.1.2 Detailed Register Descriptions Register Description Example: Index Offset Short Name Long Name Type Default Value 7 6 5 4 3 2 1 0 If the Type-box shows "rw", unused bits ("x") are not allowed to be changed: ReadModify-Write commands are necessary. 0 Bit 0 7 Index (7) 6 Index (6) Register 0 5 Index (5) 4 Index (4) 3 Index (3) 2 Index (2) 1 rw 00H 0 Index (0) Index (1) Index [7:0] Used to set the index of the page to which should be read/written. The formula to get the index value is: Index = Integer(Address/16)*8 Offset = Address - (2*index) Example: Writing to address 130. Index = INT(130/16)*8 = 64 Offset = 130 - (2*64) = 2 Data Sheet 57 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 0 Bit 1 7 MET 6 RING Register 1 5 THR 4 TONE 3 SIA1 2 SIA0 1 SIOD1 Programming r 00H 0 SIOD0 This register is used for signalling which interrupt has caused a HI -> LOW transition on the INT line. All interrupts will have the granularity of 125 s. Faster events can not be detected safely. A read operation will clear this register and sets the INT pin back to inactive (high) SIOD0 SIOD0 = 0 SIOD0 = 1 SIOD1 SIOD1 = 0 SIOD1 = 1 SIA0 SIA0 = 0 SIA0 = 1 SIA1 SIA1 = 0 SIA1 = 1 TONE Tone = 0 Tone = 1 THR Signals interrupt on change of pin RINGIND/SIOD0 (ANIC-D) when configured as input. No interrupt detected. Interrupt detected. Signals interrupt on change of pin SIOD1 (ANIC-D) when configured as input. No interrupt detected. Interrupt detected. Signals interrupt on change of pin SI0 (ANIC-A). No interrupt detected. Interrupt detected. Signals interrupt on change of pin SI1 (ANIC-A). No interrupt detected. Interrupt detected. Signals interrupt on tone detection (see register 5 for indication which tone was detected). No interrupt detected. Interrupt detected. Signals interrupt on line reversal, disconnect or 50 Hz metering signals (see register 4 for indication which line voltage passed threshold) THR = 0 THR = 1 No interrupt detected. Interrupt detected. Data Sheet 58 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary RING Ring = 0 Ring = 1 MET MET = 0 MET = 1 Programming Signals interrupt on valid ring or ring threshold depending on bit RING_VAL in register 10. No interrupt detected. Interrupt detected. Signals interrupt on the rising edge of the metering event. No interrupt detected. Interrupt detected. 0 Bit 2 7 6 Register 2 5 4 E_ TONE 3 2 1 rw 00H 0 E_ SIOD0 E_MET E_RING E_THR E_SIA1 E_SIA0 E_ SIOD1 Maskregister for interrupts E_x E_x = 0 E_x = 1 Ignore (mask) according interrupt Enable according interrupt Note: For SIA0, SIA1, RINGIND/SIOD0 and SIOD1 the correct pin values will be shown in register 5 even if the interrupt is disabled. This makes it possible to find out the level at the input pins by polling. Data Sheet 59 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 0 Bit 3 7 0 6 0 Register 3 5 0 4 0 3 2 1 Programming rw 00H 0 State(3) State(2) State(1) State(0) This register is used to program ANIC operating states: Please note that the external hook switch is handled automatically by default when changing between the operating states (bit HOOK_CMD register 31 = 0). For details on the external circuitry please refer to the Application Note "Understanding the External Components of the ANIC Chip Set". State [3:0] State [3:0] = 0000 State [3:0] = 0001 State [3:0] = 0011 State [3:0] = 0100 State [3:0] = 0101 State [3:0] = 0110 all others IDLE PULSE COMMAND CONVERSATION ON-HOOK RECEIVE ON-HOOK CONVERSATION RING internal use only Data Sheet 60 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 0 Bit 4 7 RG(1) 6 RG(0) Register 4 5 TG(1) 4 TG(0) 3 TR(3) 2 TR(2) 1 TR(1) Programming r 00H 0 TR(0) This register is used for the indication of threshold values. The value is updated if a measured voltage passes the actual programmed threshold value. This threshold indication can be masked in register 23. Masked indications are held '0' all the time. Reading this register by the host clears the register to 0x00. The voltage range is 0 to 5 V in 2s complement. TR(x) TR(x) = 0 TR(x) = 1 Programmed threshold value for TIP-RING voltage wasnt passed. Programmed threshold value for TIP-RING voltage was passed. TG(x)] TG(x) = 0 TG(x) = 1 Programmed threshold value for TIP-GROUND voltage wasnt passed. Programmed threshold value for TIP-GROUND voltage was passed. RG(x) RG(x) = 0 RG(x) = 1 Programmed threshold value for RING-GROUND voltage wasnt passed. Programmed threshold value for RING-GROUND voltage was passed. Data Sheet 61 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 0 Bit 5 7 MET 6 RING Register 5 5 TONE (1) 4 TONE (0) 3 SIA1 2 SIA0 1 Programming r 00H 0 SIOD1_I SIOD0_I This register is used for indication of ring, tone and input values. The values are updated if the according event occurs. For the tones this indication can be masked in register 24. Masked indications are held '0' all the time. Reading this register by the host clears the tone indication bits no.4 and no.5 to '0'. SIOD0_I SIOD0_I = 0 SIOD0_I = 1 SIOD1_I SIOD1_I = 0 SIOD1_I = 1 SIA0 SIA0 = 0 SIA0 = 1 SIA1 SIA1 = 0 SIA1 = 1 TONE(x) TONE(x) = 0 TONE(x) = 1 Digital input value on general purpose input/output pin RINGIND/SIOD0 (ANIC-D) Input value at pin RINGIND/SIOD0 below TTL threshold. Input value at pin RINGIND/SIOD0 above TTL threshold. Digital input value on general purpose input/output pin SIOD1 (ANIC-D) Input value at pin SIOD1 below TTL threshold. Input value at pin SIOD1 above TTL threshold. Digital input value on pin SI0 (ANIC-A, galvanic isolated) Input value on pin SI0 below TTL. Input value on pin SI0 above TTL threshold. Digital input value on pin SI1 (ANIC-A, galvanic isolated) Input value on pin SI1 below TTL threshold. Input value on pin SI1 above TTL threshold. Programmed tone (x) was detected. No tone detected. Tone was detected. Data Sheet 62 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary RING RING = 0 RING = 1 MET MET = 0 MET = 1 Programming Signals either ring threshold or valid ring, depending on RING_VAL in register 10. Ring off Ring on Signals if metering signal is present. Metering signal off Metering signal on Data Sheet 63 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 0 Bit 6 7 SOA3 Output values SIOD0_O The value of this bit is put out on the general purpose input/ output pin RINGIND/SIOD0 (ANIC-D), if programmed as output. SIOD0_O = 0 Voltage at pin RINGIND/SIOD0 greater than VDD - 0.5 V SIOD0_O = 1 Voltage at pin RINGIND/SIOD0 below 0.5 V SIOD1_O The value of this bit is put out on the general purpose input/ output pin SIOD1 (ANIC-D), if programmed as output. SIOD1_O = 0 Voltage at pin SIOD1greater than VDD - 0.5 V SIOD1_O = 1 Voltage at pin SIOD1below 0.5 V SOD0 SOD0 = 0 SOD0 = 1 The value of this bit is put out on the general purpose output pin METIND/SOD0 (ANIC-D). Voltage at pin METIND/SOD0 greater than VDD - 0.5 V Voltage at pin METIND/SOD0 below 0.5 V 6 SOA2 Register 6 5 SOA1 4 SOA0 3 x 2 SOD0 1 Programming r 00H 0 SIOD1_O SIOD0_O SOA0 SOA0 = 0 SOA0 = 1 The value of this bit is put out on the general purpose output pin SO0 (ANIC-A, galvanic isolated output). Voltage at pin SO0 greater than VDD - 0.5 V Voltage at pin SO0 below 0.5 V Data Sheet 64 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary SOA1 Programming The value of this bit is put out on the general purpose output pin SO1Q on (ANIC-A, galvanic isolated output). Note that SO1Q is a inverted output which shows high if programmed to '0'. SOA1 = 0 SOA1 = 1 SOA2 SOA2 = 0 SOA2 = 1 SOA3 Voltage at pin SO1Q below 0.5 V Voltage at pin SO1Q greater than VDD - 0.5 V The value of this bit is put out on the general purpose output pin SO2 (ANIC-A, galvanic isolated output). Voltage at pin SO2 greater than VDD - 0.5 V Voltage at pin SO2 below 0.5 V The value of this bit is put out on the general purpose output pin SO3Q on (ANIC-A, galvanic isolated output). Note that SO3Q is a inverted output which shows high if programmed to '0'. SOA3 = 0 SOA3 = 1 Voltage at pin SO3Q below 0.5 V Voltage at pin SO3Q greater than VDD - 0.5 V 0 Bit 7 7 MTR7 6 MTR6 Register 7 5 MTR5 4 MTR4 3 MTR3 2 MTR2 1 r 00H 0 MTR0 MTR1 Measurement result TIP-RING, can be polled all the time Data Sheet 65 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 0 Bit 8 7 MRG7 6 MRG6 Register 8 5 MRG5 4 MRG4 3 MRG3 2 MRG2 1 MRG1 Programming r 00H 0 MRG0 Measurement result RING-GROUND, can be polled all the time Example: If * CRAM coefficient B0h/0Fh = 52h and B0h/0Eh = 10h (see Table 9) * default measurement resolution = 5 V (see register 25) then * at + 5 V M2-M3 voltage the measurement result is 0111 1111 * at - 5 V M2-M3 voltage the measurement result is 1000 0000 Table 13 shows 8 bit measurement results obtained at different resolutions set in register 25 for exemplary M2-M3 voltages of + 0.5 V, 0 V and - 0.5 V. Table 13 Measurement Result Examples Result Resolution M2-M3 Voltage + 0.5 V 0V - 0.5 V 0.625 V + 0.5 V 0V - 0.5 V Result Resolution 1) M2-M3 Voltage 2) 5V + 0.5 V 0V - 0.5 V 3) 0000 1101 0000 0000 1111 0011 0011 0100 0000 0000 1100 1010 2.5 V 0001 1010 0000 0000 1110 0100 0110 1000 0000 0000 1001 0110 1.25 V + 0.5 V 0V - 0.5 V 1) 2) 3) see register 25 Voltage between pins M2 and M3 of PSB 4450 (peak value). Voltage at - 0.5 V is 2s complement of voltage on + 0.5 V Data Sheet 66 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 0 Bit 9 7 MTG7 6 MTG6 Register 9 5 MTG5 4 MTG4 3 MTG3 2 MTG2 1 MTG1 Programming r 00H 0 MTG0 Measurement result TIP-GROUND, can be polled all the time Data Sheet 67 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 0 Bit 10 7 PULSE 6 CMD_ MODE Register 10 5 PCM_ LOOP 4 RING_ VAL 3 DCDC 2 1 Programming rw 00H 0 ANIC-A_ SIOD1_ SIOD0_ LOOP C C Configuration of GPIO, sampling rate and testloops. SIODx_C SIODx_C = 0 SIODx_C = 1 ANIC-A_LOOP ANIC-A_LOOP = 0 ANIC-A_LOOP = 1 DCDC DCDC = 0 DCDC = 1 RING_VAL RING_VAL = 0 Configuration of pin SIODx as input or output. Pin SIODx works as input Pin SIODx works as output Loop back PCM data via ANIC-A. Loop back disabled Loop back enabled Switch DCDC clock (2 MHz) to DCDC_CLK pin Logic 0 on DCDC_CLK pin DCDC clock is switched to DCDC_CLK pin Enables software check if signal is a valid ring Ring signal detection in ANIC-A only, a signal above the threshold of 7 V will cause a RING interrupt. Checking in ANIC-D if signal is a valid ring according to amplitude and frequency defined by CRAM coefficients. Loop back PCM data via PCM Interface PCM_LOOP = 0 PCM_LOOP = 1 Loop back disabled Loop back enabled RING_VAL = 1 PCM_LOOP Data Sheet 68 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary CMD_MODE CMD_MODE = 0 CMD_MODE = 1 PULSE PULSE = 0 PULSE = 1 Stay in current power mode Automatic change between power modes enabled. Mode change only by command. Low impedance dialing pulse: operational only in pulse command mode (PULSE_CMD, register 5). No pulse ("Break") Pulse ("Make") Programming 0 Bit 11 7 0 6 0 Register 11 5 TS5 4 TS4 3 TS3 2 TS2 1 TS1 rw 00H 0 TS0 Number of timeslots per PCM frame, value 0x00 disables PCM Interface 0 Bit 12 7 0 6 0 Register 12 5 RS5 4 RS4 3 RS3 2 RS2 1 rw 00H 0 RS0 RS1 Receive timeslot in PCM frame, value 0x00 disables PCM Interface 0 Bit 13 7 0 6 0 Register 13 5 XS5 4 XS4 3 XS3 2 XS2 1 XS1 rw 00H 0 XS0 Transmit timeslot in PCM frame, value 0x00 disables PCM Interface Data Sheet 69 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 0 Bit 14 7 16K 6 OS2 Register 14 5 OS1 4 OS0 3 COMP 2 A/MU 1 x Programming rw 00H 0 EDGE PCM configuration register EDGE EDGE = 0 EDGE = 1 A/MU A/MU = 0 A/MU = 1 COMP 0 1 OS2, OS1, OS0 000 ... 111 16k 0 1 eight data clock periods added Selects the sampling mode 8 k sampling mode selected (sampling rate = 6 to 12 kHz) 16 k sampling mode selected (sampling rate = 12 to 24 kHz) Selects falling or rising edge for data transmit or receive. Receive slope with falling edge, transmit slope with rising edge. Receive slope with rising edge, transmit slope with falling edge. Selects compression law -Law selected A-Law selected Enables compander 16-Bit PCM, no Compander used 8-Bit PCM, Compander used PCM-Offset in number of data-clock periods one data clock period added Data Sheet 70 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 0 Bit 15 7 TR0(7) 6 TR0(6) Register 15 5 TR0(5) 4 TR0(4) 3 TR0(3) 2 TR0(2) 1 TR0(1) Programming rw 00H 0 TR0(0) Threshold value for THR interrupt for TIP-RING voltage Nr. 0 Note: For all threshold values the same range as for the measurement results defined in register 25 is considered. To give an interrupt for the according threshold, the bits in register 23 serve as enable bits besides the general enable bit in register 4. 8 Bit 0 7 TR1(7) 6 TR1(6) Register 16 5 TR1(5) 4 TR1(4) 3 TR1(3) 2 TR1(2) 1 rw 00H 0 TR1(0) TR1(1) Threshold value for THR interrupt for TIP-RING voltage Nr. 1 8 Bit 1 7 TR2(7) 6 TR2(6) Register 17 5 TR2(5) 4 TR2(4) 3 TR2(3) 2 TR2(2) 1 rw 00H 0 TR2(0) TR2(1) Threshold value for THR interrupt for TIP-RING voltage Nr. 2 8 Bit 2 7 TR3(7) 6 TR3(6) Register 18 5 TR3(5) 4 TR3(4) 3 TR3(3) 2 TR3(2) 1 rw 00H 0 TR3(0) TR3(1) Threshold value for THR interrupt for TIP-RING voltage Nr. 3 Data Sheet 71 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 8 Bit 3 7 TG0(7) 6 TG0(6) Register 19 5 TG0(5) 4 TG0(4) 3 TG0(0) 2 TG0(0) 1 TG0(0) Programming rw 00H 0 TG0(0) Threshold value for THR interrupt for TIP-GROUND voltage Nr. 0 8 Bit 4 7 TG1(7) 6 TG1(6) Register 20 5 TG1(5) 4 TG1(4) 3 TG1(3) 2 TG1(2) 1 rw 00H 0 TG1(0) TG1(1) Threshold value for THR interrupt for TIP-GROUND voltage Nr. 1 8 Bit 5 7 RG0(7) 6 RG0(6) Register 21 5 RG0(5) 4 RG0(4) 3 RG0(3) 2 RG0(2) 1 rw 00H 0 RG0(0) RG0(1) Threshold value for THR interrupt for RING-GROUND voltage Nr. 0 8 Bit 6 7 RG1(7) 6 RG1(6) Register 22 5 RG1(5) 4 RG1(4) 3 RG1(3) 2 RG1(2) 1 rw 00H 0 RG1(0) RG1(1) Threshold value for THR interrupt for RING-GROUND voltage Nr. 1 Data Sheet 72 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 8 Bit 7 7 E_RG(1) Programming Register 23 6 E_RG(0) rw 4 3 E_TR(3) 00H 0 E_TR(0) 5 E_TG(1) 2 E_TR(2) 1 E_TR(1) E_TG(0) Configuration of threshold interrupts E_TR(x) E_TR(x) = 0 E_TR(x) = 1 E_TG(x) E_TG(x) = 0 E_TG(x) = 1 E_RG(x) E_RG(x) = 0 E_RG(x) = 1 Enable the according threshold indication in register 4 (TIP-RING voltage threshold) Threshold indication disabled Threshold indication enabled Enable the according threshold indication in register 4 (TIP-GROUND voltage threshold) Threshold indication disabled Threshold indication enabled Enable the according threshold indication in register 4 (RING-GROUND voltage threshold) Threshold indication disabled Threshold indication enabled Data Sheet 73 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 8 Bit 8 7 6 Register 24 5 4 3 x 2 x 1 x Programming rw 00H 0 TEST_ TONE E_ E_ SHOW_ SHOW_ TONE(1) TONE(0) RING MET General Configurations TEST_TONE TEST_TONE = 0 TEST_TONE = 1 E_TONE(0) E_TONE(0) = 0 E_TONE(0) = 1 Enables the test tone generation. Level and frequency are determined by coefficients. Test tone generation off Test tone generation on Enables the tone detection of tone 0 Disable the tone detection. The according indication in register 5 will remain '0'. Enable the tone detection. Detected tones are indicated in register 5. Enables the tone detection of tone 1 Disable the tone detection. The according indication in register 5 will remain '0'. Enable the tone detection. Detected tones are indicated in register 5. Enables metering indication No metering indication The metering signals are signalled via indication on pin METIND/SOD0. E_TONE(1) E_TONE(1) = 0 E_TONE(1) = 1 SHOW_MET SHOW_MET = 0 SHOW_MET = 1 Data Sheet 74 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary SHOW_RING SHOW_RING = 0 SHOW_RING = 1 Enables ring indication No ring indication The ring is signalled via indication on pin RINGIND/ SIOD0, if configured as output (SIOD0_C = 1 in register 10). Signals either ring threshold or valid ring, depending on RING_VAL in register 10. Programming Data Sheet 75 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 8 Bit 9 7 0 6 0 Register 25 5 RG1 4 RG0 3 TG1 2 TG0 1 TR1 Programming rw 00H 0 TR0 Configuration for measurement resolution at TIP-RING, RING-GROUND and TIPGROUND. Since the measurement results stored in register 7 to register 9 are only 8 bit values the actually measured internal result of 16 bit is shifted according this bits. This configuration affects the values in register 7 to register 9 and register 15 to register 22. TR[1:0] TR[1:0] = 00 TR[1:0] = 01 TR[1:0] = 10 TR[1:0] = 11 TG[1:0] TG[1:0] = 00 TG[1:0] = 01 TG[1:0] = 10 TG[1:0] = 11 RG[1:0] RG[1:0] = 00 RG[1:0] = 01 RG[1:0] = 10 RG[1:0] = 11 Measurement resolution at TIP-RING 5 V (bit 15 to 8 of the 16 bit measurement value) 2.5 V (bit 14 to 7 of the 16 bit measurement value) 1.25 V (bit 13 to 6 of the 16 bit measurement value) 0.625 V (bit 12 to 5 of the 16 bit measurement value) Measurement resolution at TIP-GROUND 5 V (bit 15 to 8 of the 16 bit measurement value) 2.5 V (bit 14 to 7 of the 16 bit measurement value) 1.25 V (bit 13 to 6 of the 16 bit measurement value) 0.625 V (bit 12 to 5 of the 16 bit measurement value) Measurement resolution at RING-GROUND 5 V (bit 15 to 8 of the 16 bit measurement value) 2.5 V (bit 14 to 7 of the 16 bit measurement value) 1.25 V (bit 13 to 6 of the 16 bit measurement value) 0.625 V (bit 12 to 5 of the 16 bit measurement value) Data Sheet 76 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 8 Bit 10 7 RG_ PER(7) 6 RG_ PER(6) Register 26 5 RG_ PER(5) 4 RG_ PER(4) 3 RG_ PER(3) 2 RG_ PER(2) 1 RG_ PER(1) Programming rw 01H 0 RG_ PER(0) Ring persistance time in steps of 1 ms: Time from detecting a ring depending on register 10 to the signalling of a ring interrupt. If the ring disappears during this time, no interrupt is signalled. This functionality helps to suppress short rings. Note: Minimum ring persistance time is 1 ms. 8 Bit 11 7 RG_ DEG(7) 6 RG_ DEG(6) Register 27 5 RG_ DEG(5) 4 RG_ DEG(4) 3 RG_ DEG(3) 2 RG_ DEG(2) 1 rw 01H 0 RG_ DEG(0) RG_ DEG(1) Ring deglitch time in step of 1 ms to prevent detecting noise on line as ring. Note: Minimum ring deglitch time is 1 ms. 8 Bit 12 7 MET_ PER(7) 6 MET_ PER(6) Register 28 5 MET_ PER(5) 4 MET_ PER(4) 3 MET_ PER(3) 2 MET_ PER(2) 1 rw 01H 0 MET_ PER(0) MET_ PER(1) Metering signal and tone persistance in steps of 1 ms. If a detected tone or metering signal disappears during this time, no interrupt is signalled. This functionality helps to supress tone or metering signal interrupts during transients of the system. Data Sheet 77 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 8 Bit 13 7 6 Register 29 5 4 3 2 1 Programming r 01H 0 MMPER MMPER MMPER MMPER MMPER MMPER MMPER MMPER (7) (6) (5) (4) (3) (2) (1) (0) Measurement persistance time for indication of threshold passing in steps of 1 ms. If a voltage on the line passes a threshold level then this time is waited before an interrupt is signalled to avoid spike indications. 8 Bit 14 7 6 Register 30 5 4 3 2 1 r 12H 0 Hw_ver Hw_ver Hw_ver Hw_ver Sw_ver Sw_ver Sw_ver Sw_ver (3) (2) (1) (0) (3) (2) (1) (0) Software and hardware version of ANIC-D. Sw_ver[0:3] Hw_ver[0:3] Output of ANIC-D software version Output of ANIC-D hardware version Data Sheet 78 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 8 Bit 15 7 x 6 x 5 x Register 31 4 x 3 x 2 RING_ EXT 1 HOOK_ CMD Programming r 00H 0 PCM_MM PCM_MM PCM_MM = 0 PCM_MM = 1 HOOK_CMD Allows voice or measurement data to be switched to the PCM Interface. Voice-data are switched to PCM Interface (default). Measurement-data are switched to PCM-Interface. Enables automatic or host controlled handling of the hook switch. HOOK_CMD = 0 Automatic handling of hook switch during stateswitch (default). HOOK_CMD = 1 Host must handle the hook switch. RING_EXT RING_EXT = 0 RING_EXT = 1 Enables internal or external ring impedance. Ring impedance is synthezied by ANIC in RING state (default). Exernal ring impedance must be used in RING state. Data Sheet 79 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 16 Bit 0 7 x 6 0 Register 32 5 DC_K3 4 DC_K2 3 DC_K1 2 DC_K0 1 DC_U1 Programming rw 00H 0 DC_U0 DC-characteristic, provided with CRAM Coefficients. DC_U[1:0] DC_U[1:0] = 00 DC_U[1:0] = 01 DC_U[1:0] = 10 DC_U[1:0] = 11 DC_K[2:0] DC_K[2:0] = 000 DC_K[2:0] = 001 DC_K[2:0] = 010 DC_K[2:0] = 011 DC_K[2:0] = 100 DC_K3 DC_K3 = 0 DC_K3 = 1 U0 (DCU) value, see also Table 16. 0V 2.5 V 1V 3.1 V R value, see also Table 17. 100 200 280 560 1000 ILIM value, see also Table 15. min 100 mA 50 mA typ 110 mA 55 mA max 120 mA 60 mA condition TA = 0 C to 70 C TA = 0 C to 70 C Data Sheet 80 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 16 Bit 1 7 x 6 0 Register 33 5 0 4 0 3 XAGX_ K1 2 1 Programming rw 00H 0 XAGX_ RAGR_ RAGR_ K0 K1 K0 Transmit and receive gain, provided by CRAM Coefficients RAGR_K0,1 Receive gain in PSB 4450 block RAGR_K0,1 = 00 0 dB RAGR_K0,1 = 01 - 3.5 dB RAGR_K0,1 = 10 6 dB RAGR_K0,1 = 11 2.5 dB XAGX_K0,1 Transmit gain in PSB 4450 block XAGX_K0,1 = 00 - 12 dB XAGX_K0,1 = 01 - 18 dB XAGX_K0,1 = 10 - 8.5 dB XAGX_K0,1 = 11 - 14.5 dB Data Sheet 81 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 48 Bit 7 7 RING_ TO(7) 6 RING_ TO(6) Register 103 5 RING_ TO(5 4 RING_ TO(4) 3 RING_ TO(3) 2 RING_ TO(2 1 RING_ TO(1) Programming rw 0AH 0 RING_ TO(0) Ring timeout in steps of 10 ms to ensure constant detection of the ring signal in case of a short interruptions without generating a new interrupt. Default value is 100 ms. 48 Bit 8 7 MET_ TO(7) 6 MET_ TO(6) Register 104 5 MET_ TO(5 4 MET_ TO(4) 3 MET_ TO(3) 2 MET_ TO(2 1 rw 03H 0 MET_ TO(0) MET_ TO(1) AC, metering and tone timeout in steps of 1 ms to ensure constant detection of the respective signal in case of a short interruptions without generating a new interrupt. Default value is 3 ms. Data Sheet 82 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 96 Bit 12 7 0 6 COT2 Register 204 5 DHPR2 4 MM 3 FSC16 2 COT1 1 COR2 Programming rw 50H 0 COR1 DSP flags, provided by CRAM coefficients. This flags are modified automatically according to the power states. COR1 COR1 = 0 COR1 = 1 COR2 COR2 = 0 COR2 = 1 COT1 COT1 = 0 COT1 = 1 FSC16 FSC16 = 0 FSC16 = 1 MM MM = 0 MM = 1 DHPR2 DHPR2 = 0 DHPR2 = 1 Cut off receive path 1 Off On Cut off receive path 2 Off On Cut off transmit path 1 Off On Enables 16 kHz decimation Off On Enables measurement decimation Off (transparent mode) On Disable high pass receive Off On Data Sheet 83 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary COT2 COT2 = 0 COT2 = 1 Cut off transmit path 2 Off On Programming Data Sheet 84 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 96 Bit 13 7 ALF 6 IM Register 205 5 FRR 4 FRX 3 AR 2 AX 1 RIP Programming rw 3CH 0 0 DSP flags, provided by CRAM coefficients. This flags are modified automatically according to the power states. RIP RIP = 0 RIP = 1 AX AX = 0 AX = 1 AR AR = 0 AR = 1 FRX FRX = 0 FRX = 1 FRR FRR = 0 FRR = 1 IM IM = 0 IM = 1 Enables level metering and ring impedance Off On Gain transmit Off On Gain receive Off On Frequency response transmit Off On Frequency response receive Off On Impedance matching Off On Data Sheet 85 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary ALF ALF = 0 ALF = 1 Close 8 kHz analog loop Off On Programming Data Sheet 86 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 96 Bit 14 7 LPX 6 LPR Register 206 5 TG 4 LM2 3 LM1 2 LB64 1 LBZ Programming rw D8H 0 TH DSP flags, provided by CRAM coefficients. This flags are modified automatically according to the power states. TH TH = 0 TH = 1 LBZ LBZ = 0 LBZ = 1 LB64 LB64 = 0 LB64 = 1 LM1 LM1 = 0 LM1 = 1 LM2 LM2 = 0 LM2 = 1 TG TG = 0 TG = 1 Trans hybrid filter Off On Loop back via impedance path Off On Loop back at 64 kHz sampling rate Off On Level metering tone 1 (for modem tone detection and on-hook signalling from CO) Off On Level metering tone 2 (for modem tone detection and on-hook signalling from CO) Off On Tone generator Off On Data Sheet 87 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary LPR LPR = 0 LPR = 1 LPX LPX = 0 LPX = 1 Programming Enable programmable low pass receive characteristic Off On Enable programmable low pass transmit characteristic Off On Data Sheet 88 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 96 Bit 15 7 EN_TB 6 0 Register 207 5 RGS 4 MET_ MMG 3 DHPTH 2 0 1 DHPR1 Programming rw 10H 0 DHPX DSP flags, provided by CRAM coefficients. This flags are modified automatically according to the power states. DHPX DHPX = 0 DHPX = 1 DHPR1 DHPR1 = 0 DHPR1 = 1 DHPTH DHPTH = 0 DHPTH = 1 MET_MMG Disable high pass transmit Off On Disable high pass receive 1 Off On Disable high pass trans hybrid Off On Enable metering signal detection and measurement gain MET_MMG = 0 Off MET_MMG = 1 On EN_TB EN_TB = 0 EN_TB = 1 RGS RGS = 0 RGS = 1 Enable low pass in ring path Off On Level metering frequency response transmit Off On Data Sheet 89 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Programming 128-184 Bit 7 0-15 6 CRAM 5 CRAM Register 256 - Register 383 4 CRAM 3 CRAM 2 CRAM 1 rw 00H 0 CRAM CRAM CRAM CRAM Coefficients Data Sheet 90 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Operating Modes 7 7.1 Table 14 Mode Operating Modes Operating Modes of ANIC System Operating Modes Impedance to the Line AC and DC high ohmic System Power safe, ready for setup (transition state, not a valid powermode) RING level metering Receiving and transmitting of data without DC impedance. After ring detection, automatic switch to ring mode. Receiving of data without DC impedance. After ring detection, automatic switch to ring mode. Receiving and transmitting of data with DC impedance. On-hook Modes IDLE RING Ring impedance via AC loop ON-HOOK AC impedance, high DC resistance CONVERSATION ON-HOOK RECEIVE AC and DC high ohmic Off-hook Modes CONVERSATION AC impedance & DC resistance PULSE COMMAND "Make" or "Break" according to the PULSE bit (register10) without current limitation. In this chapter the basic operation modes will be explained. Each operating mode can be entered by a command. Data Sheet 91 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Operating Modes 7.2 7.2.1 On-hook RESET (Basic Setting Mode) Condition: RESET pin ='0', external master clock can be inactive. The PSB 4451 has no internal power on reset. For valid operation the power must be asserted and after that an active low RESET (minimum length tRESET,min = 300 ns) must be given to the chip. Since all control is done via a controller in the chip a "boot" time of ~ 2000 cycles is necessary to get into an stable operation mode. The first mode after reset is IDLE. In this mode only the setup of the chip is possible (read and write registers). Registers will be reseted to the default values. Note: As all information is stored within PSB 4451 and permanently transferred to PSB 4450, a power on reset of PSB 4450 will NOT force PSB 4450 into the basic setting mode, as it is reprogrammed immediately to its former power state by PSB 4451. 7.2.2 IDLE Mode Condition: RESET pin = '1', external master clock active. Will be entered after reset. The coefficients must be downloaded to ensure proper functionallity in all other modes. Only the digital interface of the ANIC is active in this mode. ANIC will send a maskable interrupt on any change of a GPI pin. Note: IDLE is not a valid powermode for the PSB 4450 (entered only after reset). 7.2.3 RING Mode Condition: RESET pin = '1', external master clock active In this mode, a valid ring can be signalled by an interrupt depending on the RING_VAL bit. The programmed Ring impedance will be synthesized. ANIC will also measure the voltage between TIP-RING, TIP-GND and RING-GND. Tone detection, measurement-threshold interrupts and changes of the GPI pin will be indicated by maskable interrupts. 7.2.3.1 RING - Automatic State Transitions Valid ring is signalled Ring threshold is signalled Automatic Mode 1: Automatic Mode 2: Data Sheet 92 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Operating Modes If the line voltage is higher than the ring threshold and ANIC is in on-hook mode, it is immediately switched to RING state and sets a deglitched ring signal bit. Depending on the programmed mode there are two possibilities: a.) signal ring only if valid: the DSP checks the frequency and level of the believed ring signal and signals only valid rings to the host. b.) signal any ring: any voltage higher than the threshold is immediately signalled as a ring indication to the host. Ring signal on TIP-RING Threshold ON-HOOK RING ON-HOOK Ringdetect (analog ring) Timeout Ring (internal) Ring deglitch time Timeout Degliched ring Ring persistance time Valid ring Ring persistance time signal any ring at INT pin signal any ring at RINGIND/SIOD0 pin signal valid ring at INT pin signal valid ring at RINGIND/SIOD0 pin RING_VAL = 1 RING_VAL = 0 here the ring is signalled if valid detection is done by the Host here the ring is signalled if valid detection is done in ANIC here the ring end is signalled ezm33014.emf Figure 30 Ring Detect Note: If ANIC is not in any on-hook mode and a ring interrupt is received, the first task of the interrupt service routine should be to switch the system into the RING mode to prevent damage of the ANIC-A. Data Sheet 93 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Operating Modes 7.2.4 ON-HOOK CONVERSATION Mode Condition: RESET pin = '1', external master clock active The programmed AC impedance for on-hook transmission will be synthesized. ANIC is able to receive and transmit voice or data. So an incoming CLIP (Calling Line Identification Presentation) will see the programmed AC impedance and will be transmitted to the selected PCM timeslot. ANIC will also measure the voltage between TIP-RING, TIP-GROUND and RING-GROUND. If a ring occurs ANIC will enter the Ring Mode. Tone detection, metering, measurement-threshold interrupts and changes of the GPI pin will be indicated by maskable interrupts. 7.2.5 ON-HOOK RECEIVE Mode Condition: RESET pin = '1', external master clock active ANIC is able to receive voice and data. So an incoming CLIP (Calling Line Identification Presentation) will see a high AC impedance and will be transmitted to the selected PCM timeslot. ANIC will also measure the voltage between TIP-RING, TIPGROUND and RING-GROUND. If a ring occurs ANIC will enter the Ring Mode. Tone detection, metering, measurement-threshold interrupts and changes of the GPI pin will be indicated by maskable interrupts. 7.3 7.3.1 Off-hook CONVERSATION Mode Condition: RESET pin = '1', external master clock active The programmed DC characteristic will be synthesized. An AC impedance can be programmed. ANIC is able to receive and transmit voice. ANIC will also measure the voltage between TIP-RING, TIP-GROUND and RING-GROUND. The metering signal detection is signalled via interrupt. Tone detection, metering, measurement-threshold interrupts and changes of the GPI pin will be indicated by maskable interrupts. For going on-hook, on of the three valid operating modes ON-HOOK RECEIVE, ON-HOOK CONVERSATION or RING has to be selected. 7.4 PULSE COMMAND Mode It is possible to implement the pulse dialing by alternating between a short and a high ohmic impedance on TIP and RING. The pulse duration for "Make" and "Break" (see register 10) must be controlled by the external host (C). Data Sheet 94 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Characteristics 8 8.1 Electrical Characteristics Programmable Filters A set of programmable filters is used to adapt the whole system to: * country standards * board designs (EMI capacitors etc.) * telephone lines 8.2 DC Characteristics Within the following chapter the DC performance of the ANIC will be described. 8.2.1 DC Termination The DC termination is enabled in off-hook mode and disabled during on-hook mode. The DC Termination can be programmed according the formula: for ITIP-RING < ILIM: ITIP-RING(UTIP-RING) = (UTIP-RING - U)/R for ITIP-RING = ILIM: ITIP-RING(UTIP-RING) = ILIM Note: U is the sum of the U0 value (see Table 16) and the flow voltage of the diodes in the external bridge (typ. 2 x 0.7 V) plus all other external components inserted in series into the loop. UTIP-RING ILIM R U ITIP-RING ezm25010.wmf Figure 31 Data Sheet DC Termination Characteristics 95 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Characteristics 8.2.2 Table 15 Programming Ranges for DC Termination Selectable Values for ILIM ILIM1) 55 mA 110 mA 1) for temperature depency see Page 80. Table 16 0V 1V 2.5 V 3.1 V Table 17 95 Selectable Values for U0 U0 (DCU) Selectable Values for R R (DCR) 190 270 530 960 Data Sheet 96 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary 70 Electrical Characteristics UTIP-RING [V] 52.5 35 ILIM 17.5 U 0 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 ITIP-RING [A] ezm33007.wmf Figure 32 DC Characteristics for France The diagram above shows the programmed DC feeding characteristics ITIP-RING (with U0 = 2,5 V , R = 200 , ILIM = 55 mA ) of the ANIC chip set to fulfill the ILIM requirements according to france telecommunication standards. 8.2.3 Line Current in PULSE COMMAND Mode Uab = 30 V DC Parameter Input current at break Symbol Iin - Limit Values min - typ max < 500 A Unit Data Sheet 97 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Characteristics 8.3 8.3.1 AC Termination Ringer Impedance Uab = 70 Vrms Parameter Ringer impedance (10 Hz < f < 80 Hz)1) Typical capacitors 1) 2) Symbol Limit Values min typ - - max 8 3 2 1.5 Unit k F RIN CIN2) Ringer impedance is generated only in ring mode. Values achievable with two external capacitors of each 3.3 F. 8.4 DC Measurement Parameter Symbol min - Limit Values typ - - - 8 3% 1% max Bit Unit Resolution Absolut error Relative error VIN VIN - - 8.4.1 Ring Detect Levels and Frequencies Parameter Symbol Vring 10 - 10 Limit Values min typ - - - max 150 5 80 V V Hz Unit Tolerance Programmable range for ring-level detection Ring-level detection step size Programmable range for frequency detection 10% 10% 10% Vring Fring Data Sheet 98 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Characteristics 8.4.2 On-hook and Off-hook Settling Time Parameter Symbol 1) 1) Limit Values min typ - - max 0.5 0.5 - - Unit ms ms Tolerance Time off-hook to on-hook Time on-hook to off-hook 1) tON tOFF Time from CS to until loop current is above or below 15 mA, for 8 or 16 kHz sampling frequency only. Data Sheet 99 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Performance Characteristics 9 Electrical Performance Characteristics Functionality and performance is guaranteed for TA = 0 C to 70 C by production testing. Extented temperature range operation at - 40 C < TA < 85 C is guaranteed by design, characterization and periodically sampling and testing production devices at the temperature extremes. 9.1 Absolute Maximum Ratings Parameter Symbol Ratings min max 4.6 5.5 7.0 10.3 100 150 85 1 V V V V mA C C W - 0.3 - 0.3 - 0.3 - 0.3 - - 55 - 40 - Unit Supply voltage PSB 4451 Input voltages PSB 4451 Supply voltage PSB 4450 Input voltages PSB 4450 DC input and output current (free from latch-up) Storage temperature Ambient temperature under bias Max. power dissipation VDD VDIN VDDA VIN Iin , Iout TST TA PDmax Note: Stresses above the absolute maximum ratings may cause permanent damage to the device. Extended operation at maximum levels may degrade performance and affect reliability. Data Sheet 100 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Performance Characteristics 9.2 Recommended Operating Conditions Parameter Symbol min Conditions typ 3.3 5.0 25 25 24.576 50 - max 3.6 5.25 110 125 33 55 10 V V C C MHz % ns 3.0 4.75 - 40 - 40 16.384 45 - Unit Digital supply voltage PSB 4451 Analog supply voltage PSB 4450 Ambient temperature under bias Junction Temperature Operating frequency Clock duty cycle Signal rise and fall time VDD VDDA TA TJ fMCLK - tr, tf Note: Extended operation outside the recommended limits may degrade performance and affect reliability. Data Sheet 101 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Performance Characteristics 9.3 9.3.1 DC Characteristics PSB 4450 VDDA = 5 V 5 %; TA = - 40 C to 85 C, unless otherwise stated. Table 18 DC Characteristics PSB 4450 Symbol tPU - Conditions - - - Spec. Limits min Power-up time Supply Current IDLE mode ON-HOOK CONVERSATION and ON-HOOK RECEIVE modes RING mode CONVERSATION mode Digital Interface Low-level input voltage - 2.5 17 typ max 100 3 20 ms mA mA Unit Parameter IDDA1 IDDA2 Vring = 60 Vdc + 90 Vrms, fring = 25 - 50 Hz VTIP-RING = 30 Vdc IDDA4 IDDA5 - - - - - - - 2.0 - 3.25 - - - - - - - - - - 10 10 0.8 - 0.5 - 1 1 mA mA V V V V VIL High-level input voltage VIH Low-level output voltage VOL High-level output voltage VOH Input current low IIL Input current high IIH Input Resistance DC On-hook: IDLE mode RING mode Off-hook: Pulse dialing CONVERSATION mode Power supply rejection IOL = 5 mA IOH = - 5 mA VIL = VGNDA VIH = VDDA A A RIN 200 V - - 11) M RIN RIN PSRR Inter-pulsing period (make) - Ripple: 0 - 150 kHz; 70 mVrms - - - - 200 - W W Data Sheet 102 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Table 18 Electrical Performance Characteristics DC Characteristics PSB 4450 (Continued) 300 Hz - 3.4 kHz 40 - - - - dB dB 3.4 kHz - 150 kHz 25 either supply/direction either supply/direction 1) Higher impedances can be achived by the use of an external hook switch (see Application Note "Understanding the External Components of the ANIC Chip Set") Data Sheet 103 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Performance Characteristics 9.3.2 PSB 4451 VDD = 3.3 V 5 %; TA = - 40 C to 85 C, unless otherwise stated. All digital inputs are 5 V tolerant. Table 19 DC Characteristics PSB 4451 Symbol Conditions Spec. Limits min Supply Current IDLE mode ON-HOOK CONVERSATION and ON-HOOK RECEIVE modes RING mode CONVERSATION mode Low-level Input Voltage - at CMOS Inputs: VIL1 RINGIND/SIOD0, SIOD1, CS, DCLK , DIN, DATCLK, DATIN, FSC, RESET - at clock Input: MCLK1 High-level Input Voltage - at CMOS Inputs: VIH1 RINGIND/SIOD0, SIOD1, CS, DCLK , DIN, DATCLK, DATIN, FSC, RESET - at clock Input: MCLK1 Low-level Output Voltage - at pins: DOUT, INT, VOL1 DATOUT, FSC, DATCLK, DCDCCLK - at pins: SIOD1, METIND/SOD0 - 2.0 - 5.5 V - 0 - 0.8 V typ 11 22 max 15 30 mA mA Unit Parameter IDD0 IDD1 no load VDD = 3.3 V - fMCLK = 25 MHz - IDD3 IDD4 - - 22 22 30 30 mA mA VIL2 - - 0.2 V - 0.8 V VIH2 - 2.5 - VDD + V 0.2 IOL1 = 5 mA - - 0.5 V VOL2 IOL2 = 2.5 mA - - 0.5 V Data Sheet 104 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Table 19 Electrical Performance Characteristics DC Characteristics PSB 4451 (Continued) High-level Output Voltage - at pins: DOUT, VOH1 DATOUT, FSC, DATCLK, DCDCCLK - at pins: SIOD1, METIND/SOD0 Input Current Low - at CMOS inputs: IIL RINGIND/SIOD0, SIOD1, CS, DCLK , DIN, DATCLK, DATIN,FSC, RESET Input Current High - at CMOS Inputs: IIH RINGIND/SIOD0, SIOD1, CS, DCLK , DIN, DATCLK, DATIN, FSC, RESET Tristate Current Low Tristates, Bidirectionals: IOZL DOUT1), DATCLK, DATOUT1), SIOD1, FSC, INT2) Tristate Current High Tristates, Bidirectionals: IOZH DOUT1), DATCLK, DATOUT1), SIOD1, FSC, INT2) 1) 2) IOH1 = - 5 mA VDD - 0.5 - - V VOH2 IOH2 = - 2.5 mA VDD - 0.5 - - V VIL = VGND - - 1 A VIH = VDD - - 1 A VIL = VGND - - 1 A VIH = VDD - - 1 A 660 k internal pull-up resistor (range 330 k to 2 M)=not taken into consideration. 33 k internal pull-up resistor (range 16.5 k to 100 k)=not taken into consideration. Data Sheet 105 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Performance Characteristics 9.4 AC Transmission Characteristics Unless otherwise stated, the transmission characteristics are guaranteed within the following test conditions: TA = - 40 C to 85 C VDD = 3.3 V 5 % VDDA = 5 V 5 % Line impedance ZL = 600 0.1 % Termination impedance ZM = 600 digital: 0 dBm0 = - 3.14 dB FS analog: 0 dBm is equal to the voltage of 0.775 Vrms when loaded with 600 f = 1014 Hz. AGR = 0 dB, AGX = - 8.5 dB Note: Informations on degradiation due to extended temperature range is available on request. 9.4.1 Absolute Gain Error Off-hook Parameter Symbol AE_R - 0.3 0.2 0.3 - 0.3 0.3 0.3 AE_X - 0.3 0.2 0.3 - 0.3 0.3 0.3 dB dB dB dB - 10 dBm0 Limit Values min typ max - 10 dBm Unit Test Condition Absolute gain error receive TA = 25 C; VDDA = 5 V TA = 0 - 70 C; VDDA = 5 V Absolute gain error transmit TA = 25 C; VDDA = 5 V TA = 0 - 70 C; VDDA = 5 V Data Sheet 106 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Performance Characteristics 9.4.2 Absolute Gain Error On-hook Parameter Symbol AE_R - 0.5 0.2 0.5 - 0.5 0.3 0.5 - 0.5 0.2 0.5 - 0.5 0.3 0.5 dB dB - 10 dBm0 dB dB Limit Values min typ max - 10 dBm Unit Test Condition Absolute gain error receive TA = 25 C; VDDA = 5 V TA = 0 - 70 C; VDDA = 5 V Absolute gain error transmit AE_X TA = 25 C; VDDA = 5 V TA = 0 - 70 C; VDDA = 5 V Data Sheet 107 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Performance Characteristics 9.4.3 Gain Tracking Off / On-hook 2 dB 1.4 1 0.5 0.25 0 -0.25 -0.5 -1 -1.4 -2 -70 -60 -55 -50 -40 -37 -30 -20 -10 3 0 dBm0 10 G Input level ezm07272.emf Figure 33 Gain Tracking Off / On-hook (Receive or Transmit) Note: measured with sine wave f = 1014 Hz, reference level is - 10 dBm(0) 9.4.4 Idle Channel Noise Symbol Limit Values min typ - - - 85 5 max - 67.4 dBm0p psophometric VIN = 0 V 17.5 dBmc C-message VIN = 0 V Unit Test Condition Parameter Idle channel noise: transmit, A-law transmit, -law receive, A-law receive, -law NTP NTC NRP NRC - - - - - 78.0 dBm0p psophometric idle code + 0 12.0 dBmc C-message idle code + 0 Data Sheet 108 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Performance Characteristics 9.4.5 Out of Band Idle Channel Noise at TIP/RING With an idle code applied to the digital input, the level of any resulting out-of-band power spectral density (measured with 3 kHz bandwidth) at the analog output, will be not greater than the limit curve shown in the figure below. -40 dBm0 -50 -60 -65 -70 -78 -80 -90 -100 10 1 10 2 10 3 kHz 10 4 f ezm07270m.emf Figure 34 Out of Band Idle Channel Noise Data Sheet 109 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Performance Characteristics 9.4.6 Harmonic Distortion plus Noise Off-hook - 10 dBm(0); ZL = 600 ; f = 1014 Hz Parameter HDN receive HDN transmit HDN receive HDN transmit 1) Symbol THDN_Rc THDN_Tc THDN_Rl THDN_Tl 74 73 72 71 Limit Values min typ - - - - max - - - - Unit dBFS dBm dBFS dBm Test condition C-weighted linear-weighted1) Linear weighted values are guaranteed by design. Characterization and periodically samples will be applied to production devices at this test conditions. 9.4.7 Harmonic Distortion plus Noise On-hook - 10 dBm(0); ZL = 600 ; f = 1014 Hz Parameter HDN receive HDN transmit HDN receive HDN transmit 1) Symbol THDN_Rc THDN_Tc THDN_Rl THDN_Tl 64 64 62 62 Limit Values min typ 67 67 65 65 max - - - - Unit dBFS dBm dBFS dBm Test condition C-weighted linear-weighted1) Linear weighted values are guaranteed by design. Characterization and periodically samples will be applied to production devices at this test conditions. Data Sheet 110 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Performance Characteristics 9.4.8 Harmonic Distortion Off-hook - 10 dBm0; ZL = 600 ; f = 100 to 2000 Hz, 2nd and 3rd harmonic Parameter HD receive HD transmit Symbol HDN_R HDN_T 80 80 80 Limit Values min typ - - - max - - - dBm0 - dBm - dBm0 - Unit Test Condition HD of echo signals via HDN_El TIP-RING The gain deviations stay within the limits in the figures below. 9.4.9 Harmonic Distortion On-hook - 10 dBm0; ZL = 600 ; f = 100 to 2000 Hz, 2nd and 3rd harmonic Parameter HD receive HD transmit Symbol HDN_R HDN_T 70 70 70 Limit Values min typ - - - max - - - dBm0 - dBm - dBm0 - Unit Test Condition HD of echo signals via HDN_El TIP-RING Data Sheet 111 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Performance Characteristics 9.4.10 Total Distortion The signal to distortion ratio exceeds the limits in the following figure. 9.4.10.1 Total Distortion Measured with Sine Wave 40 36.4 S/D dB 35.5 31 29.5 y-LAW 30 27 24.5 20 A-LAW 10 0 -60 -50 -45 -40 -30 -28 -20 -10 dBm0 0 Input level ezm07273.emf Figure 35 Total Distortion Receive or Transmit Note: measured with sine wave f = 1014 Hz (C-message weighted for -law, psophometrically weighted for A-law). Data Sheet 112 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Performance Characteristics 9.4.10.2 Total Distortion Measured with Noise According to CCITT 40 S/D dB 30 36.3 35.4 33.3 28.7 27.4 20 13.7 10 0 -60 -55 -50 -40 -34 -30 -27 -24 -20 dBm0 -10 -6 -3 0 Input level ezm07275.emf Figure 36 Total Distortion Receive 40 36.7 S/D dB 34.3 30 29.7 36 28.4 20 14.7 10 0 -60 -55 -50 -40 -34 -30 -27 -24 -20 dBm0 -10 -6 -3 0 Input level ezm07274.emf Figure 37 Data Sheet Total Distortion Transmit 113 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Performance Characteristics 9.4.11 Return Loss The return loss at a level of 0 dBm0 is better than 16 dB in a 300 - 3600 Hz bandwidth within the following range of AC impedances: ZAC = 500 - 1500 (0 to - 30). dB 20 16 TBRL 300 500 Frequency (f) 2500 3400 Hz ezm25015.emf Figure 38 Return Loss Data Sheet 114 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Performance Characteristics 9.4.12 Frequency Response The following tables and diagrams are for on-hook transmission as well as for off-hook transmission. 9.4.12.1 Receive Reference frequency 1014 Hz, input signal level - 10 dBm 2 Attenuation dB 1 0.650 dB 0.125 dB 0 -0.125 dB -1 0 0.1 0.2 0.3 1 2 3 3.2 3.4 Frequency kHz ezm25000.wmf Figure 39 Frequency Response Receive Data Sheet 115 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Performance Characteristics 9.4.12.2 Transmit Reference frequency 1014 Hz, input signal level - 10 dBm 2 Attenuation dB 1 0.650 dB 0.125 dB 0 -0.125 dB -1 0 0.2 0.3 1 2 3 3.2 3.4 Frequency kHz ezm25001.wmf Figure 40 Frequency Response Transmit (HPX is off) Data Sheet 116 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Performance Characteristics 9.4.13 Group Delay Group delay is per definition1) the time of propagation between two points of a certain point (e.g. the crest) of the envelope of a wave. For a given frequency it is equal to the first derivative of the phase shift measured in radians, between these points, with reference to the angular frequency measured in radians per second. Group Delay remains within the limits in the figures below. 9.4.13.1 Group Delay Absolute Values Parameter Receive delay Transmit delay Symbol DRA DXA - - Limit Values min - - typ max 340 400 s s Input signal level 0 dBm0 Unit Reference The absolute group delay refers to the minimum group delay measured in the frequency band 500 Hz - 2800 Hz. 9.4.13.2 Group Delay Distortion Taking as the reference the minimum group delay, in the frequency range between 500 Hz and 2800 Hz, of the receive or transmit connection, the group delay distortion of that connection should lie within the limits shown in Figure 41 and Figure 42. Group delay distortion is measured in accordance with ITU-T Recommendation O.81. 1) from CCIT Blue Book, Volume 1, Fascicle 1.3 "Terms and Definitions. Abbreviations and Acronyms". Data Sheet 117 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Group Delay Distortion Receive Input signal level - 10 dBm Electrical Performance Characteristics 500 s TG 400 300 200 100 85 0 0 0.5 0.6 1.5 2.5 2.6 2.8 3.5 Frequency kHz ezm25002.wmf Figure 41 Group Delay Distortion Receive Group Delay Distortion Transmit Input signal level - 10 dBm0 500 s TG 400 300 200 100 85 0 0 0.5 0.6 1.5 2.5 2.6 2.8 3.5 Frequency kHz ezm25003.wmf Figure 42 Group Delay Distortion Transmit Data Sheet 118 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Performance Characteristics 9.4.14 Out-of-Band Signals at TIP-RING Receive When an 0 dBm0 out-of-band sine-wave signal with a frequency of << 100 Hz or 3.4 kHz to 100 kHz) is applied to the analog input, the level of any resulting frequency component at the digital output will stay at least X dB below a 0 dBm0 (1014 Hz sine wave reference signal at the analog input.1)) 40 Attenuation dB 35 32 30 25 20 15 10 0 0 0.06 0.1 3.4 4.0 4.6 6.0 10.0 18.0 100 Frequency kHZ ezm25004.wmf Figure 43 Out of Band Receive Discrimination 1) Poles at 12 kHz 150 Hz and 16 kHz 150 Hz will be provided Data Sheet 119 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Performance Characteristics 9.4.15 Out-of-Band Signals at TIP-RING Transmit When a 0 dBm0 sine wave with a frequency of (300 Hz to 3.99 kHz) is applied to the digital input, the level of any resulting out-of-band signal at the analog output will stay at least X dB below a 0 dBm0 1014 Hz sine-wave reference signal at the analog output. 60 Attenuation dB 50 45 40 35 30 28 20 15 10 0 0 0.06 0.1 3.4 4.0 4.6 6.0 8.0 10.55 10.0 16.0 18.0 1000 Frequency kHZ ezm25005.wmf Figure 44 Out of Band Transmit Discrimination 9.4.16 Trans-Hybrid Loss Parameter Symbol Limit Values min THL 300 THL 500 THL2500 THL3000 THL3400 27 33 29 27 27 typ - - - - - dB dB dB dB dB Unit Test Condition Trans-hybrid loss at 300 Hz 500 Hz 2500 Hz 3000 Hz 3400 Hz TA = 25 C; VDDA = 5 V; The listed values for THL correspond to a typical variation of the signal amplitude and delay in the analog blocks. Amplitude = typ. 0.8 dB Delay = typ. 0.5 s Data Sheet 120 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Performance Characteristics 9.4.17 Metering Detection Sensibility U [mV] 10500 detection possible detection 5500 2600 1400 100 50 14 15 15,5 no detection 16 17 18 f [kHz] ezm25016.wmf Figure 45 Metering Detection Sensibility 16 kHz (Typical) U [mV] 10500 detection possible detection 5500 2600 1400 100 50 10 11 11,5 no detection 12 13 14 f [kHz] ezm25017.wmf Figure 46 Metering Detection Sensibility 12 kHz (Typical) Data Sheet 121 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Performance Characteristics 9.5 9.5.1 AC Timing Characteristics Input/ Output Waveform for AC Tests O u tp u t P a d : Device under test VD D - 0.5 V 0.5 V 2.0 V 0.8 V T e st P oin ts 2.0 V 0.8 V IO L , IO H CLo ad = 50 pF m ax In p u t P a d : Device under test VIL , VIH ezm37010.emf Figure 47 Waveform for AC Tests During AC-Testing, the CMOS inputs are driven at a low level of 0.8 V and a high level of 2.0 V. The CMOS outputs are measured at 0.5 V and VDD - 0.5 V respectively. 9.5.2 Reset Timing To reset the ANIC, pulses applied to the RESET pin must be less than 0.8 V and longer than tRESET,min (300 ns). Pulses shorter than tRESET,ignore (60 ns) are ignored. RESET t R E S E T ,m in 0 .8 V (VIL1 ) alis_0036_reset_timing.emf Figure 48 Reset Timing Data Sheet 122 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Performance Characteristics 9.5.3 Serial Control Interface Timing CS t SU(CS) t C(DCLK) DCLK tHD(CS) t SU(DIN) DIN DOUT Figure 49 t HD(DIN) t D(DOUT) t D(DOUT_Z) HIGH IMPEDANCE ezm25007.emf Serial Control Interface Timing Data Sheet 123 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary . Electrical Performance Characteristics Serial Control Interface Switching Characteristics Table 20 VDD = 3.3 V 5 %; TA = - 40 C to 85 C, unless otherwise stated. DCLK doesnt need to have a constant frequency Parameter DCLK cycle time DCLK duty cycle DCLK frequency (SCI-Clock fDCLK) Setup time: CS until next DCLK= Hold time: last DCLK=until CS Setup time: DIN valid before DCLK Hold time: last DCLK=until DIN invalid Delay time: DCLK=until DOUT valid Delay time: last DCLK until DOUT_Z (when DOUT goes to tristate) at IOL1 = 5 mA Symbol min tC(DCLK) - - tSU(CS) tHD(CS) tSU(DIN) tHD(DIN) tD(DOUT) tD(DOUT_Z) 488 45 1 - 50 - Limit Values typ max 106 55 2048 - - - - 20 40 ns % kHz ns ns ns ns ns ns Unit 2*TMCLK - 2*TMCLK - 20 20 - 5 - - - 10 Note: Internal pull-up resistor at DOUT: 660 k (range 330 k to 2 M). Data Sheet 124 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Electrical Performance Characteristics 9.5.4 PCM Interface Timing t C(FSC) tW(FSC) FSC tSU(FSC) t C(DATCLK) DATCLK t SU(DATIN) DATIN DATOUT Figure 50 t HD(DATIN) t D(DATOUT) t D(DATOUT_Z) HIGH IMPEDANCE ezm25013.emf PCM Interface Timing Note: DATOUT goes to tristate on the last bit of 8 or 16 bits transferred in a FSC frame before DATOUT switches to high impedance. Data Sheet 125 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Table 21 Electrical Performance Characteristics PCM Interface Switching Characteristics VDD = 3.3 V 5 %; TA = - 40 C to 85 C, unless otherwise stated. The last data bit of a certain timeslot on DATOUT changes to tristate after approximately tC(DATCLK) / 2. Parameter DATCLK (PCM-Clock) cycle time DATCLK (PCM-Clock) duty cycle DATCLK (PCM-Clock) frequency Frame Synchronization Clock (FSC) cycle time FSC frequency FSC pulse width (as input) Setup time: DATIN valid before DATCLK Symbol tC(DATCLK) - - tC(FSC) - tW(FSC) tSU(DATIN) 488 45 512 83 6 20 20 - 4*TMCLK Limit Values min - 50 - 125 8 - - - - 10 typ max 1953 55 2048 166 12 - - - 20 - 40 ns % kHz s kHz ns ns ns ns ns ns Unit tC(DATCLK) - Hold time: last DATCLK=until=DATIN tHD(DATIN) invalid Delay time: DATCLK until DATOUT tD(DATOUT) valid Setup time: FSC until next DATCLK Delay time: last DATCLK until DATOUT_Z (when DATOUT goes to tristate, LSB only) at IOL1 = 5 mA tSU(FSC) tD(DATOUT_Z) 5 Note: Internal pull-up resistor at DATOUT: 660 k (range 330 k to 2 M) Data Sheet 126 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Application Circuit 10 Application Circuit For an application circuit see our Application Note "Understanding the External Components of the ANIC Chip Set". Data Sheet 127 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Package Outlines 11 Package Outlines P-TSSOP38 PSB 4450 (Plastic Thin Shrink Small Outline Package) Gps09158.eps P-TSSOP28 PSB 4451 (Plastic Thin Shrink Small Outline Package) Gps05867.eps Sorts of Packing Package outlines for tubes, trays etc. are contained in our data book "Package Information". SMD = Surface Mounted Device Data Sheet 128 Dimensions in mm 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Glossary 12 ADC ANIC CLIP CO CODEC CRAM DAA DAC DLC DSL DSP EMC FCC GPI GPO Mbits/s MDSL MLT MUX PCM PBX VDD CI, SCI Glossary Analog-to-Digital Converter Analog Network Interface Circuit Calling Line Identification Presentation Central Office Coder/Decoder Coefficient RAM Data Access Arrangement Digital-to-Analog Converter Digital Loop Carrier Digital Subscriber Line Digital Signal Processing Electro Magnetic Compatibility Federal Communications Commission General Purpose Input General Purpose Output Mega Bits Per Second Mid-rate Digital Subscriber Line Mechanical Loop Testing Multiplexer Pulse Code Modulation Private Branch Exchange Voltage Drain Drain Serial Control Interface Data Sheet 129 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Index 13 A Index I Idle Mode 60, 91, 92, 102 Impedance matching 36, 85 Indexed addressing mode 48, 49, 57 Inductive interface 50 Interrupt-Handling 26 Analog-to-Digital Converter 20, 23 ANICOS software 24, 25, 36 C Capacitive interface 50 Central Office Terminal 19 Coefficient RAM 19, 21, 45, 53 Conversation Mode 60, 91, 94, 102, 104 CRAM Coefficients 80, 83, 85, 87, 89, 92 Current feeding 21 L Level Metering 37, 85, 87, 91 Line Reversal 24, 58 M Master Clock 17, 38 Measurement persistance 78 resolution 76 result 65 Ring-Ground 66 Tip-Ground 67 Tip-Ring 65 Measurement persistance 78 Metering 23, 25, 37, 74, 77, 89 indication 18 interrupt 32 signal 13 D Data Access Arrangement 12, 13 DC Characteristic 13, 36, 94, 95, 97 ILIM value 80, 95 R value 80, 95 U0 value 80, 95 DC measurement 13, 24, 98 Digital Added Main Line 11 Digital isolation interface 19, 20, 36, 50 Digital Loop Carrier 11 Digital-to-Analog Converter 20 DSP flags 83, 85, 87, 89 Dynamic Interrupts 33 O Off-hook Mode 95, 108, 110 On-hook Conversation Mode 60, 91, 94, 102, 104 Mode 95, 107, 108, 110, 111 Receive Mode 60, 91, 94, 102, 104 Transmission 13 F Frame Synchronization Clock 17, 39, 126 Frame synchronization clock (FSC) 104, 105 G Group Delay Receive 117 Transmit 117 P PBX trunk 11 PCM Interface 17, 19, 21, 23, 38, 68, 125 Frames 44 Single Clock Rate 43 Polarity reversal 12 H Hardware filters 21 Hardware version 78 Hybrid circuit 20 Data Sheet 130 2000.09.04 PSB 4450 / PSB 4451 ANIC Preliminary Polling Ring Interrupt 29 Threshold Interrupts 34 Pulse Command Mode 60, 91, 94, 97 Pulse dialing 102 pulse 69 Index R Receive gain 81, 85 Reset 17, 92, 122 Ring deglitch 77 detection 13, 25, 91 impedance 23, 85, 92, 98 indication 18, 62, 75 Mode 60, 91, 92, 102, 104 persistance 77 S Sampling rate 68 16 kHz 40, 70 8 kHz 40, 70 Serial Control Interface 17, 19, 21, 38, 45, 123 Read Access 46 Write Access 45 Software version 78 Static Interrupts 27 T Testloops 68 ANIC-A loop 36 PCM loop 36 Time slot assignment 12 Tone detection 24, 58, 62, 74, 92, 94 Tone generator 24, 74, 87 Trans hybrid 87, 120 Transmit gain 81, 85 V Voltage sensing 21 Data Sheet 131 2000.09.04 Infineon goes for Business Excellence "Business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction." Dr. Ulrich Schumacher http://www.infineon.com Published by Infineon Technologies AG |
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